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ISO5500 Conflicting Statements?

Fig 66 suggests that an  AND GATE is not required to reset the fault latch.

Fig 67 suggests that the AND GATE is required to reset the fault latch.

Will the circuit of Fig 66 reset the fault latch?

Dick Wood

motcontrol@outlook.com

  • Hi Dick,

    From my reading of the datasheet, the circuit in Fig 66 is used when the application requires that the Fault signal be cleared on a cycle by cycle basis without any intervention from the controller.

    The circuit is Fig 67 requires the uC to issue a RESET signal in the event that a FAULT signal is received.

    Regards

    Peter