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TPS54561-Q1: Low-dropout 100% duty cycle operation

Part Number: TPS54561-Q1
Other Parts Discussed in Thread: TPS54561EVM-555, TPS54561

Hi

We want to use TPS54561-Q1 in a design where the nominal input voltage is 24 -28.5 and the output is 12V

To verify the design I have modified a TPS54561EVM-555 to output 12V. Our design looks like the attached shematic and the TPS54561EVM-555 is modified to match it.

The system where the TPS54561 is used need to pass some pretty hard cranking tests which means the regulator input can go down to 8 V.

When I tested to lower the input voltage to the modified evel board (loaded with 1.75A), it started to behave strange when the input voltage droped below 12.5V (buzzing noise from the circuit and increased output noise by 300 - 400 mV). This behaviour is quite as expected (except the buzzing noise) when reading about low dropout behavoiur and 100 % duty cycle in the datasheet when the gate driver needs to recharge tp keep the FET open.

But when the input voltage drops below 8.5V the circuit starts "ticking" (the buzzing sound is still there) and the output voltage has 5V drops with a repetition rate of 10Hz.

What can I expect from the TPS54561 when I drop the input voltage below the regulated output voltage? Can my identified behaviour be explained?

Is there any way to make the output voltage just follow the input voltage (with som drop) in this condition?

Regards

/Johan

  • Can you post waveforms of normal operation Vin = 24 V, drop out Vin = 10 V, and your problem voltage, Vin < 8,5 V/ Be sure to include Vout, SW and COMP pin voltages. Make sure the time scale is such that we can see the individual SW node pulses.
  • Ok, I will try to capture some waveforms tomorrow and post them.
    But can anything be said about how I could expect the TPS54561 to bahave under these conditions?

    Regards
    /Johan
  • Hi

    I have attached 3 waveforms.

    Vin = 8.2V has two waveforms. One zoomed in on the SW edge and one showing the low frequency dip on the output voltage.

    Yellow = COMP

    Purple = Vout

    Blue = SW

    Regards

    /Johan

  • I'll discuss this with my colleague and get back to you later today.

  • This is not what we were expecting.  Form your third waveform, it looks like your circuit is shutting down and restarting.  You will need to zoom in on the falling edge of Vout and look at VIN, EN and SS/TR.  You might also want to look at BOOT relative to SW as well.  Let's see if we can figure out why the device is restarting.  It may be possible you have a thermal issue.  Can you post your PCB layout? 

  • Hi

    Yes you where right about that the circuit is restarting. I did some measurements you suggested and I found out that SS/TR was ramping and also that Vin was also falling when Vout was falling. My conclusion was that my powert source could not supply the amount of current needed when the input voltage was dropping and approaching 8V. I found another power source with 10A capability and then the behaviour in the third waveform was gone.

    Now the circuit behaves quite as expected even with voltages under 8V. The only anoying thing is that the circuit is "buzzing" with voltages belov 12.5V

    I have modified an evaluation board (TPS54561EVM-555) so thats the PCB layout.

    Is this baviour with the boot capcitor recharge at low input voltages the only way to design the circuit? I was thinking about if the boot pin could be connected in some other way so that the FET could be held open all the time insted of forcing the circuit to switch to recharge the boot cap?

    Regards

    /Johan