Hello.
I have some questions about capacitor selection. (Please see Figure 28 of TPS51120 data sheet.)
(1)
If a capacitor of 1 uF is selected as in the data sheet for C51, the capacitance will be 0.575 uF due to the DC bias characteristic of 5 V. Is there a problem with this capacitor? Or is it better to select 2.2uF, which has a 5V bias characteristic close to 1uF?
・ 1uF: Murata, GRM155R61H105KE05D -> DC bias characteristics 0.575uF (5V)
・ 2.2uF: Murata, GRM155R61E225KE11D -> DC bias characteristics 1.196uF (5V)
(2) C30 and C50 should be 4.7uF or more according to Data Sheet 10.1 Layout Guide Line. Is it necessary to be 4.7uF or more in consideration of DC bias characteristics? Considering that, there is no problem with selecting the following?
C30: Murata, GRM188R61A226ME15D(22uF) -> DC bias characteristics 8.242uF (3.3V)
C50: Murata, GRM188R61A226ME15D(Same as C30) -> DC bias characteristics 5.175uF (5V)
(3) I want to secure an output capacitor of 47uF with a ceramic capacitor. However, considering the DC bias characteristics, it has become necessary to connect two 47 uF ceramic capacitors in parallel.
In the design of TPS51120, the ESR of the output capacitor affects the calculation of ripple current and so on. However, I think that there is no problem because the combined ESR decreases because the capacitors are connected in parallel. Is that idea correct?
