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UCC24612: Gate - Source Waveform from controller

Thomas Relling
Prodigy 50 points

Part Number: UCC24612

Why is the gate - source voltage > 20 V in the SIMPLIS simulation when The Functional Block Diagram shows the highest voltage is 9.5V due to a linear regulator?

Why can't SIMPLIS complete a POP Analysis with the UCC24612?  I get an error saying there is a problem with a C10 internal to the UCC24612.

See the attached PowerPoint for the details.

Thanks!Errors with UCC24612 Simulation.pptx

  • 0
    TI__Mastermind 40580 points

    Hello Thomas,

    Thank you for your interest in the UCC24612 SR controller.

    The gate drive gets its charge from the REG node inside the IC, and is normally 9.5V.  In your simulation set-up, however, you have set an initial condition of 22V on the REG filter cap C3.  So the VG output will follow the REG voltage from 22V down to 9.5V eventually, as the charge is transferred from C3 to the Fet gate over many switching cycles.  I recommend that you set IC for C3 to 8V, and IC for C1 to 10V (which is your bias source voltage).

    The POP error message indicates that it is unable to find a repetitive value for an internal capacitor C10.  I was able to investigate this cap and found that it is a timer cap of 1pF charged by a 1uA current source to a 2.2V threshold on a comparator that discharges it with a 1-ohm transistor.  I believe that this sub-circuit can achieve a periodic value but requires more than 20 cycles to settle to the satisfy the POP accuracy criteria.  These criteria can be changed in the POP analysis dialog box.  I recommend that you either increase the number of cycles allowed to find the POP or reduce the required accuracy of the repeating value, or both.

    Regards,

    Ulrich