Hi,
My customer use TPS40200 for 42V input and 5V7A output. below is their schematic and waveform of the FET drive. they think the waveform of the FET driver is not good and want to improve it. please kindly give some suggestion. thanks.
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Hi,
My customer use TPS40200 for 42V input and 5V7A output. below is their schematic and waveform of the FET drive. they think the waveform of the FET driver is not good and want to improve it. please kindly give some suggestion. thanks.
Hi Yue,
This DPAK FET is quite capacitive, hence the relatively long MIller plateau interval. Also, it is critical to minimize gate loop inductance to avoid unnecessary gate voltage ringing - hence the recommendation to route the gate and source traces as a diff pair from the controller to the FET. Also, keep the gate trace as short as possible by placing the controller close to the FET.
Regards,
Tim