What do I need to know about power up delay when designing a driver bootstrap supply?
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Minimal startup time is a key factor in designing a circuit that is both energy efficient and fast. The startup time is limited by the power up delay, defined as the time the driver is enabled to the first output. As with many circuits, the minimal power up delay for a bootstrap supply is determined by the driver used, and can be found in the datasheet. For example, UCC21520 has a typical VDDA Power-up delay time of 50us. By nature, bootstrap power supplies have an additional delay on the high-side output, as the high-side output of the driver is not enabled until the supply voltage from VDDA to VSSA reaches the UVLO level of the driver. The total power up delay, then, is the time it takes the CBoot (Highlighted in Fig. 1) to reach the UVLO level plus the typical VDDA Power-up Delay of the driver. A simulated power up delay waveform is shown in Fig. 2, as the driver is enabled at 10us and the capacitor starts charging. The output of the driver then starts responding 50us after the capacitor voltage crosses the UVLO threshold of 8V.
Figure 1: Bootstrap Supply Schematic with Bootstrap Components Highlighted
Figure 2: Typical Power Up Delay for UCC21520. C_boot = 1.1uF, R_boot = 2.2 Ohm, Freq = 1MHz, dead time = 100ns, duty cycle = 50%, V_boot = 18V
While the VDDA Power-up Delay of the driver cannot really be controlled, the delay associated with the charging of the bootstrap capacitor can be limited in two ways. The first and most effective of these is to include a programed startup sequence, as is shown in Fig. 3. Such a sequence allows the bootstrap capacitor to charge before the driver is actually needed as a result of planning for the delay. This reduces the negative consequences of power up delay.
Figure 3: Example Pre-charge Sequence
The second method is to adjust the bootstrap components. The charging time of the bootstrap capacitor is directly affected by the switching frequency, dead time, duty cycle, UVLO level, bootstrap resistance, and bootstrap capacitance. This relationship is shown in Fig. 4. However, many of these factors are predetermined by the application. The only factors that can be easily adjusted are the values of RBoot and CBoot. By minimizing the bootstrap resistance and capacitance the power up delay can be reduced. The problem with this is that both of these components have significant impact on other factors, including the high-side supply dV/dt (https://e2e.ti.com/support/power-management/f/196/t/927826), and bootstrap capacitor overcharge. Generally, these two factors require the increase of bootstrap capacitance and/or resistance. Because of this conflict, it is necessary to find a balance. Generally, it is going to be more important to limit bootstrap capacitor overcharge and high-side supply dV/dt, so the bootstrap components should be chosen at the minimum values that meet those requirements.
Figure 4: Effect of CBoot and RBoot on Power Up Delay
Best practice is to implement both of these methods for controlling the power up delay, using a pre-charge sequence as shown in Fig. 3, while still keeping RBoot and CBoot at the minimal acceptable values to meet other design requirements. When combined these two methods will both minimize the bootstrap capacitor charging time and plan for the delay by pre-charging the capacitor. If you have any further questions, feel free to click the yellow ask a related question button, and we will get back to you!
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