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[FAQ] LM5176: Using digital feedback resistor

Part Number: LM5176

My customer is using LM5176 with a digital rheostat as the lower feedback resistor to allow selectable output voltages. However, they have had some random stability/ripple issues.

Do we have any resources on using supplies with a digital feedback resistor?



  • Hello Viktorija,

    Could you please share the schematic? If you want to keep it private, please send me a friendship request.

  • Hello Viktorija,

    Thank you very much for sharing the schematic. My first comment is that I would recommend using a standard FB resistor divider and use the digital feedback resistors only to change the output voltage. The reason for this is that I fear problems if there are short periods of time when the digital resistor is open with the digital resistor being the only one from FB to GND.

    According this comment: We were seeing a ripple of around 400mV that would disappear for small bits of time.

    Would you please share some measurements of the following signals: VOUT, VIN, SW1, SW2 that we can dig into this in more detail?

  • Hi Brigitte, 

    I'm not quite sure what is meant by the "standard FB resistor divider and use the digital feedback resistors only to change the output voltage" -- is this referring to something like the setup here with the parallel resistor? (From TIDU533)

  • Hello Viktorija,

    Sorry for being unclear. Yes, exactly this is meant with using the digital potentiometer only for changing the output voltage, not setting the basic value. With this setup even if the potentiometer creates an open or short, the converter still operates properly and within the expected range.

    So Rpar makes sure that an open of the potentiometer is not a problem and Rser makes sure that a short of the potentiometer does not cause a problem.

  • Hello Viktorija,

    There is one additional point that makes it difficult to use digi pots directly on the FB node. Some have capacitance in parallel to the resistor and this capacitor is limiting the loop response time as this capacitor needs to be charged or discharged when there is a voltage change on the output.

    The above network minimizes as well the influence of this capacitor to the FB node.