This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS763-Q1: TPS76350 failed while connected with 100uF distributed load

Part Number: TPS763-Q1

Hello,

This is related question to the previous one. 

ESR mentioned in datasheet for stable operation is effective ESR (parallel combination) of all the capacitors connected at the output , correct?

For experiment, we had connected around 100uF in total (all MLCC) at all loads and source and when we powered ON. Immediately, LDO failed.

Could it be overcurrent during power ON?

Regards

Abhijith V 

  • Hi Abhijith,

    Yes, ESR requirement includes all output caps. But, keep in mind that the ESRs don't simply add, because they are modeled like this:

    I would suspect that you are correct and the device is being fried by high inrush current. There is internal current limit set, but it takes a finite amount of time for that circuit to kick in so it may be that the part is damaged before current limit can kick in. 

    Is 100uF necessary for your application or can you try reducing the total capacitance to test for failure?

    Best regards,
    Nick

  • Hello Nick,

    We put 100uF for experimentation to reduce the noise on the load side and was not design intended.

    We expected LDO might go unstable, but thought overcurrent protection would protect the component and didnt expect component to fail.

    Do you have this test(checking if overcurrent limit is working) in your component validation?

    If available, could you mention what is the failure mode of the LDO like what would be the impedance across the terminals.

    P.S: Since it was done as part of 'Design of experiments' to solve another issue, we might not spend more time in finding the root cause of LDO failure by repeating the test again. So, want to know if we can arrive at a definitive root cause by inspecting the LDO.

    Regards

    Abhijith V P

  • Hi Abhijith,

    We do not have validation data for this part; we only have char data which is already included in the EC table. I have ordered some parts to collect some data, but we are in the process of moving to a new building so I will not be able to get into the labs again until November 16. 

    Since we don't have data, maybe we can make a more educated guess given your setup for now. Can you share a schematic for the LDO and its surrounding circuitry, along with Vin(nom), Vin ramp rate? Do you have any scope shots for the startup failure event? Also, what exactly do you mean by the LDO fails? Does it just not regulate properly or is it sinking too much current?

    I've talked to one of the other experts about this and they are not so sure that this is an overcurrent issue on startup, so we will do our best to diagnose the failure mode until we can get in and test it ourselves.

    Best regards,

    Nick