This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LP5036: minimal time falling edge SCL SDA

Expert 4780 points
Part Number: LP5036

Dear Team,

LP5036 according to datasheet requires a minimal time of the falling edge of SCL and SDA of 15ns -> after some research the finding was that mmight only be valid for frequencies > 100Khz (fast-mode). Customers  only has 5ns and their frequency is at exactly 100kHz. Could that lead to problems?

Regards

Andreas

  • Hi Andreas,

    Sorry for late reply that this thread was missed by us. 5ns rising/falling time is available for LP5036 I2C interface. We have do some simulation and bench tests before that the minimum limitation is around 2ns. Also many customers used it at very fast rising/falling time and we do not received transmission issue yet. Datasheet value referred the I2C protocol standard, which limit rising/falling time at high value to prevent potential EMI issue. 

    The key spec is 5 data hold time in datasheet 7.6 section Timing Requirements. After SCL falling edge come, then SDA can change the level .