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FUSION_DIGITAL_POWER_DESIGNER: Setting GPIO via Digital Fusion on Xilinx AC701 board causes board to not power up!

Part Number: FUSION_DIGITAL_POWER_DESIGNER

I have a Xilinx AC701 board.  I am trying to set GPIO 16 and 17 to '1' via the gui.  This should change VCCO_VADJ to 3.3V.  I power up the board, bring up Digital Fusion, and then click on configure, and change the settings.  I write to hardware and then write to NVRAM.  When I cycle power, the board will not come back up.  I then have to go back and restore the configuration via provided XML files to restore the board, and bring it back to life.

I am also having issues monitoring the voltages and have played with the SSA settings per other support cases, as well and toggle the control lines via the gui, with inconsistent results!

  • Hello

    Could you share how do you configure the GPIO16 and 17 to one? Could you provided the working xml file and modified xml file(with GPIO 16/17 to one)?

    This shall help us understand the issue better.

    As for the other issue, could you provide more details so that we can better assist.

    Regards

    Yihe

  • To change the state of the GPIO as follows

    1. Power up the board with the adapter plugged in.
    2. Launch Fusion Digital Designer
    3. Click on "Click to Configure device (UCD90120 at address 102)
    4. Change Command GPO #1 and Command GPO #2 (pins 33 &34 GPIO 16 &17) to High(1)
    5. Write to hardware
    6. Store RAM to Flash
    7. Cycle power

    I do not modify import or anything else with the XML file.  Once the above procedure is completed, and I have to restore the chips using the attached XML.  Is there a way to change the XML to change the state of these GPIO.  I looked through the XML and it was not evident as to how to modify the file. (not sure how to attach the file at the moment)

  • How do I send/attach the XML file to this thread?

    You can access it at the Xilinx site here - https://www.xilinx.com/support/answers/64890.html

    Not that the board in question is the AC701 rev 2.0 

  • In looking at the XML, what would I change to have these come up at a logic "1"

    <Parameter>
    <ID>GPIO_CONFIG_16</ID>
    <Code>251</Code>
    <IDAndCode>GPIO_CONFIG_16 [MFR 43,0xFB]</IDAndCode>
    <ValueText>Enable: False; Out_Enable: False; Out_Value: False; Status: True</ValueText>
    <ValueEncoded xsi:type="PMBusByte" Hex="0x08" />
    <ParameterType>Custom</ParameterType>
    <ParameterCategory>Status</ParameterCategory>
    <Page>255</Page>
    <Phase xsi:nil="true" />
    </Parameter>
    <Parameter>
    <ID>GPIO_CONFIG_17</ID>
    <Code>251</Code>
    <IDAndCode>GPIO_CONFIG_17 [MFR 43,0xFB]</IDAndCode>
    <ValueText>Enable: False; Out_Enable: False; Out_Value: False; Status: True</ValueText>
    <ValueEncoded xsi:type="PMBusByte" Hex="0x08" />
    <ParameterType>Custom</ParameterType>
    <ParameterCategory>Status</ParameterCategory>
    <Page>255</Page>
    <Phase xsi:nil="true" />
    </Parameter>

  • Hello

    You have to understand the function of the GPIO 16/17 in the Xilinx system. what will happen when these two pins go high? You may need check Xilinx to understand these.

    The problem is not about TI Fusion GUI and it is about how the Xilinx system work with those two GPIOs.

    For the testing purpose, you can skip step 6 and 7 above. After step5, GPIO16 and GPIO17 shall go high immediately.

    if you skip step 6 and go direct to step 7, the GPIO 16/17 will default to low again.

    It is not friendly to modify xml file directly. but you can import or export the xml file. Please follow below video

    https://training.ti.com/fusion-power-designer-import-and-export-project-files?context=1136655-1139495-1136588

    Regards

    Yihe

  • Hi

    When you reply this post, there is a attachment icon and please click it to upload the file.

    I downloaded the zip file and it is the U9 xml file which has both GPIO16/17 set a LOW.

    What do you expect when these two pins go high? have you probed the signals to confirm they are HIGH afterwards?

    Regards

    Yihe

  • I have tried multiple permutations, but cannot get the GPIO to power up to a high state via modifying the XML

    <Parameter>
    <ID>GPIO_CONFIG_16</ID>
    <Code>251</Code>
    <IDAndCode>GPIO_CONFIG_16 [MFR 43,0xFB]</IDAndCode>
    <ValueText>Enable: True; Out_Enable: True; Out_Value: True; Status: True</ValueText>
    <ValueEncoded xsi:type="PMBusByte" Hex="0x08" />
    <ParameterType>Custom</ParameterType>
    <ParameterCategory>Status</ParameterCategory>
    <Page>255</Page>
    <Phase xsi:nil="true" />
    </Parameter>
    <Parameter>
    <ID>GPIO_CONFIG_17</ID>
    <Code>251</Code>
    <IDAndCode>GPIO_CONFIG_17 [MFR 43,0xFB]</IDAndCode>
    <ValueText>Enable: True; Out_Enable: True; Out_Value: True; Status: True</ValueText>
    <ValueEncoded xsi:type="PMBusByte" Hex="0x08" />
    <ParameterType>Custom</ParameterType>
    <ParameterCategory>Status</ParameterCategory>
    <Page>255</Page>
    <Phase xsi:nil="true" />
    </Parameter>

  • Hi

    Have you checked the schematics to see whether there are pull-down anywhere to prevent the pin going high?

    Regards

    Yihe

  • The Xilinx documents show that they should be high to select 3.3V operation.  As you can see from the schematics below, they switch in different sense resistors (U64) which are used to feed back the trim voltage.  I have not verified that I can make them come up as logic level high, when it locks up.  Where in the XML do you see them being set to low. I am not seeing the icon to attach file....Where is it - what does it look like?

    I have imported the XML, in off line mode, then changed the configuration of the two pins and then exported the XML, configured the device, brought up Fusion, and when I go tot he config page, they still show as coming up as low!!

  • Hi

    The UCD90120A-U9 Addr 102 Vadj 2.5vPNo-Active-Trim.xml has both GPIO 16/17 as low by default.

    Have you tried my suggest to by pass step 6 and 7?

    Whatever you change under offline mode, you have to save it first, then export as a new xml file, import the new xml to a live device. Is this what you have done?

    Please try to import the attached file which have both GPIO 16/17 default at HIGH.

    UCD90120A-U9 Addr102 Vadj 2.5V_No-Active-Trim from TI.xml

    here is the snapshot of the icon to attach file

    Regards

    Yihe

  • AC701A-U9 @ Addr 102h Project.xml

    See the above as the starting point.  From the name, it appears you may have started with an earlier version.  I will take a look at he XML changes.

    I have not tired skipping the steps you suggested and will give that a try.

  • Now I am totally confused.

    I opened the Fusion tool in off line mode. I imported the golden XML made no changes and then exported to a different name. I close the tool and reopen in offline mode and import the recently exported file.  When I then go to the configuration page, the number of IO have changed from two to four. Again, i just imported and then exported.

  • Hello

    is the file shared in the previous post gold file? if not, please share it.

    Which fusion GUI do you use here?

    We always recommend to use the latest fusion gui at https://www.ti.com/tool/FUSION_DIGITAL_POWER_DESIGNER

    Regards

    Yihe

  • Yes, I believe so, but just in case, see the attached. I downloaded the tools earlier this week, so I expect they are current. I am using version 7.4.1 of the Fusion Digital Power Designer to make the changes. I have also used it in the offline mode to try working with XML files

    It may be an issue with this board, or Xilinx.  If I use the GUI to change GPIO 16  to a '1', write to NVRAM, and cycle power, the board supplies will not come up.  If I then go back in and change it to a '0' write to NVRAM and cycle power, the board comes up.  If I program GPIO 17 to a 0 or a 1, the board comes up no problem.

    Note that I have to power down and disconnect the pod to test, as he board will not power up with the pod plugged in, in all case. Thus the need to write to NVRAM for each test.

    3323.AC701A-U9 @ Addr 102h Project.xml

  • Hello

    I tried import, export your file under offline and re-import after relaunch the offline GUI and can not duplicate the issue.

    Are you sure that you do not change anything after importing the golden xl file?

    Could you make the problem again?

    You have to contact Xilinx to understand the function of GPIO16 and why system does not power up when it is HIGH?

    Regards

    Yihe

  • Not sure file differences are really an issue, but here are import and export with no changes, with a number of file differences between the two.

    I am in contact with XIinx. Thanks

    If you could generate an xml from the AC70....XML file that has the two GPIO in question driven high, that would be appreciated.

    6332.AC701A-U9 @ Addr 102h Project.xml6724.test1.xml

  • Hello

    Please see the attached xml file with two GPIO default at HIGH.

    Regards

    Yihe6332.AC701A-U9 @ Addr 102h Project TI.xml

  • I was able to resolve the issue.  There were some additional settings that need to be set,. There was also a contention issue on the board that was resolved by removing 4 transistors, allowning for the PMBUS to be isolated from the FPGA, allowing better signal integrity for the pod.