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TPS650864: Questions about PMIC design guide

Part Number: TPS650864
Other Parts Discussed in Thread: CSD87381P,

Hi,

(I'm sorry to ask you frequently..)

We are currently analyzing the pmic performance of our board due to poor performance.

1. Compared to the TPS650864x EVM board, The EVM board found that the PGNDSNS and CSD87381P's GND were separately separated and connected to each other.

(ex. PMIC pin.40 <-> route <-> CSD87381P GND pin.3)

On our board, on the other hand, it is connected to the GND PLANE without any separation.

Can you tell us the difference between the two cases?

2. According to the datasheet, FBVOUT1 is described as follows: Connect to positive terminal of output capacitor. 

On our board, FBVOUT1 is connected with the next node of feedback resistance.

Is that the problem?

(Green : VSYS, Yellow : GPO1)

(T6508641 / PG1.0 / TI 84I / C39X G4 ??)

(Green : LDO3V3, Yellow : GPO1)

Regards,
Geonwoo

  • Hi Geonwoo,

    1. PGNDSNSx is used for current limit. If it is connected to the Thermal Pad GND rather than the LS FET GND, the current limit circuit will be less accurate, depending on the impedance between those two points on your board. During debug, you may want to try removing the ILIMx resistor to se if the current limit being inaccurate is the source of the issue, but generally I have not seen customer issues tied to this. Usually AGND tied to Thermal Pad is a larger concern as it may affect the accuracy of all rails.

    2. If this is TPS6508641 OTP, the FBVOUT1 is using external feedback so it should connect to feedback resistor as noted. The other side of R7 should connect to an output capacitor (or load input capacitor) for stabilization. I also recommend a 5 pF capacitor capacitor in parallel with R7 if you are seeing some performance issues with the 5V supply. This feedforward cap has helped a couple of folks using this part.

    If you have any scope shots of the issue, you can post with a description and I can try to help. One note from my side is that the TPS650864 family monitors all enabled rails for power faults so if you are seeing one rail turning off, chances are they all are and it can be difficult to identify which is the root cause. Generally the best way is to use I2C to ask the PMIC which rail had a PWRFAULT in the PWRFAULT registers, but if that is not easily accessible, then checking the timing of which rail is rising or falling BEFORE the GPOx go low is usually a good indicator of which rail is power faulting.

  • Thank you for your reply. I'm sorry the question didn't seem specific.

    The PMIC(TPS6508641) currently in use is working well. However, when the MPSoC is operated at full load, a problem occurs that the power is drop in a moment. If the PMIC input voltage is 8V or lower, there is no problem, and if it is more than that, the problem appears. That's why I was currently looking for reasons that don't work at voltages above 8V. (When MPSoC is operated at full load. Normally normal)

    I calculated current limit, inductance, output capacitor, input capacitor and applied the results to the board, but it had no effect. Now I'm reading the Design Guide, and I've noticed some singularities:

    1. Not all inductors, input/output caps, and FETs are on the same board layer as the IC. (Inductors, FETs, PMIC are in the same layer.)

    2. DRVLx is not routed to the same layer as ICs and FETs.

    3. PGNDSNS1,2,6 are merged with the GND Plane.

    4. The sense line is routed to the same layer as the switched line.

    5. AGND is not connected with the GND of the VREF filter capacitor.

        AGND is not connected to a dedicated ground island.

        AGND is merged with the GND Plane.

    Of the five things mentioned, I wonder if there is a fatal factor that degrades PMIC performance.

    Thank you.

  • Hi Geonwoo,

    Of the five, (1), (2), and (3) are all best practices but I have less concern for these 3 items - I have seen lots of crazy designs that don't have issue so I'm not too worried. (4) may be bad if it is routed with the SWx net but it's mostly a concern for the part where the high current is switching (large EMI) - not as much a concern if it is on the SWx sense portion. (5) seems the worst but I have not seen a failure linked to that specifically.

    Are you able to power the board up, use the MPSoC to read and clear any PMIC interrupts, then cause the board to fail & restart (I assume it restarts?) and read out from the PMIC interrupts again?

    I am still not coming up with a great reason why >8V would be worse - in general we see the opposite in most cases. Did completely removing the ILIM resistors have no impact?

  • Hi,

    1. What registers should I read? PMIC I2C is connected to the MPSoC for control.

    2. I've removed all ILIM resistors, but the results were the same. (Booting is normal. When MPSoC is operated at full load, power is drop.)

    3. The input voltage is used as the input voltage of CSD87381P in addition to VSYS. Is there anything to doubt here?

    Thank you.

  • I've debugged the PMIC interrupt register by reading it.

    before) 0x02, 0x05, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6 = 0x00

    after) 0x02 = 0x88 or 0x08 / 0x05 = 0x06 or 0x04 / 0xb2 = 0x01 or 0x10 or 0x11 / 0xb3, 0xb4, 0xb5, 0xb6 = 0x00

    PMIC input voltage 8V is connected direct through the power supply. (Sufficient supply current)

    So shutdown due to UVLO doesn't make sense...

    Anyway, Is it right to see that there's a problem with BUCK1 and BUCK5?

    (1.2V is a power source that is rarely used. So it's more confusing..)

    Thank you.

  • Hi Geonwoo,

    Will take a look tomorrow (very late my time).

    One quick note from my side is that UVLO is set every time the device is powered up (since it is by default coming from a UVLO). If you want to confirm no UVLO (low risk for this case), you could clear the interrupt during the "before" phase.

    Can you take scope shots of the output of these rails and the SW node during the failure event (trigger on a GPO going low is generally easiest if you have 3+probes)? BUCK1 failure makes me think maybe adding the feedforward cap will help. BUCK5 failure is a bit more strange - how much total capacitance is on this output? We have seen issues with >400 uF.

  • Hi,

    1. I added a feedforward cap of 27pF to BUCK1, but there was no particular difference.

    2. BUCK5 has a cap of 22uF, 100nF.

    3. The scope shot of BUCK1 SW was attached. This is the result when VSYS is 8.5V, 7.5V, 6V. (In reply, the image was not attached, so I attached it to the main question post.)

  • Hi Geonwoo,

    Thank you for testing the feedforward capacitor. 27 pF is a bit high but if you didn't see a major change in performance then I would not recommend spending more time trying other values for now.

    For BUCK5, I don't think I have test data below 2x22uF capacitors - can you try adding another 22 uF to see if it helps?

    For the SW node shots, they are too zoomed out and don't appear to be taken during a shutdown event. Please try to take the scope shot with ~5 pulses before the shutdown event (GPOx going low).

  • Hi,

    1. I added a 22uF cap to BUCK5, but there was no particular difference.

    2. I measured GPO1 and SW1 when the MPSoC is operated at full load. I don't know if it's the scope shot you need.

     

    Thank you.

  • In addition, I attach scope shot of GPO1, 3, and 4.

    Blue - GPO3, Green - GPO4, Yellow - GPO1

  • Hi Geonwoo,

    This is a the right timing, but the time scale is too large. In order to try to understand what is happening at the moment of the failure, can you adjust it to something like 1 or 2 us/div? So that you can observe the behavior of the individual pulses on SW node.

  • Hi,

    Attached the following four scope shots for SW1: 1us/div, 2us/div, 10us/div, 100us/div

    (I can't upload image to that reply.. I attached it to the main questions page.)

  • Thank you for the follow up. Looking through the scope shots, I'm not seeing any new hints to investigate. There does look to be a fair bit of noise during the mid-point of the switching but my best guess is that the probe is picking up noise from a nearby rail. To confirm, you are not seeing any signs of input voltage ringing on the VSYS pin, right?

    The switching looks regular, no sign of long pulses (instability) or changing frequency that I could tell. Is there any chance the BUCK1 FB is picking up noise from a nearby switcher? Maybe next test could be to try adding 100 nF in parallel with R8 to see if that helps?

  • Yes, VSYS does not change in this situation. (Attached it to main page)

    As you said, I connected 100nF in parallel to R8. But there is no difference.

    And BUCK1 FB noise? I don't know what it means. I'm sorry.

  • Hi Geonwoo,

    Thank you for the post - it looks like the GPO is ramping down before shutting off which is interesting. Is it pulled up to LDO3P3? 

  • Hi,

    LDO3P3 is not pulled up.

    When designing the TPS6508641, I referenced AVNET Ultra96 V1 EVM schematic.

  • Hi Geonwoo,

    To clarify, I mean do you have GPO1 with a pull-up resistor to LDO3P3? If LDO3P3 is shutting down at any point, the PMIC digital logic can't be trusted. The image you posted had GPO1, but the voltage seems to have 3 different levels, an initial level, a minimum right before shut-off, and a maximum after restarting. If GPO1 is pulled up to LDO3P3, which is what I expect for Ultra96, then this would potentially indicate an issue with LDO3P3:

     

    Could you take a picture of the top of the PMIC showing the symbolization? I know we have been working on this for a while, I wanted to check when the silicon you are using was manufactured. 

    If this is indeed showing LDO3P3 voltage, can you take a scope shot of the LDO3P3 output similar to above to confirm it has the same shape? Or any other abnormality? 

  • Hi,

    1. GPO1 is pulled up to LDO3P3.

    2. I attached picture of the top of PMIC to main page.

    3. I attached LDO3V3 to main page.

  • Very interesting - that LDO3P3 behavior looks real strange.

    Can you confirm all the nets connected to LDO3P3? The most common reason for this kind of LDO3P3 droop with no VSYS droop would be too much load on LDO3P3. 

    Does this happen on multiple units and all the time? 

  • Hi,

    All nets to which LDO3V3 is connected are almost same as Ultra96. There is no other connected place.(Used as a pull-up of CTL1,3,4,6, PMIC I2C CLK/DATA, GPO1, 4. And there is a net associated with LTC2954CDDB-1TRMPBF, but it is in the DNP.)

    The current problem only appears when MPSoC is operated at full load.

  • Hi Geonwoo,

    To confirm, how many total boards do you have?

  • Thank you.

    I'm struggling to come up with a reason that LDO3P3 would droop when MPSoC is operating full load, but only having issues when input voltage is above 8V. Can you provide the board layout? 

  • Hi,

    I will send the layout file to private message.

    Full layout is hard to share. So I'll send only the PMIC area.

    Thank you for your hard work.

  • Hi Geonwoo,

    Thank you for sending over the layout. I have done a full review (messaged back to you). I'll summarize some key points as well as some next steps at the bottom.

    Major:

    1. The LDO3P3 has a large output plane, nearly all of L6-P is LDO3P3. This is a small internal LDO with pretty limited load capability. The plane can be picking up noise very easily and feeding that back into the PMIC. [AI#1]
    2. Buck converters (3/4/5) input has too few vias if you are using more than 1A
    3. Buck controllers (1/2/6) FET GND has only 1 via each, not sufficient for >1A
    4. LDOA1 output plane is large and above BUCK2. We recently solved an issue where they were picking up noise on the LDOs leading to power fault eventually. Adding a resistive pull down prevented build up of noise (will discuss more in next setps)
    5. LDOA2 and LDOA3 have smaller planes, but may be worth trying on those as well, especially LDOA2 since it has that big test point right above the noisy power pad.
    6. Specifically looking at things that might be an issue at higher input voltages, the only thing that really jumped out at me was that the capacitances used at the 7V input are all very close to the bare minimum and increasing voltage will derate them significantly. 
    7. The prioritization of components isn't great. For example, the I2C pin pull-up resistors are on the same layer as the PMIC right next to the PMIC, while the LDO3P3 and LDO5P0 output caps are on bottom. The I2C pull-ups can be anywhere and are very low priority, while the output caps are #2 priority behind only input caps.

    Minor:

    1. Generally we recommend avoiding thermal relief, it likely has marginal impact but it is adding a small amount of resistance/inductance which we prefer to avoid.

    Potential next steps (in order from easiest to hardest)

    1. Add pull-down resistance to LDOA1, LDOA2, and LDOA3, target 50 mA - the goal here is if there is noise being injected on these, they have no way to pull down the output resistance so adding a discharge path helps
    2. Increase capacitance on all nets related to 7V (VSYS, BUCK1/2/6 input) - they are all very marginal. The 47 uF cap for example derates by 77% at 8V: http://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL31A476MPHNNN 
    3. Cut LDO3P3 from the LDO3P3 plane, connect it to an output capacitor, supply the plane from an external supply
      1. This one is pretty tough but seems the most likely issue to me. 
  • Hi,

    I really want to thank you for your help.

    The board is so small that I don't know if i can apply the things you said. But I'll try to reflect as much as possible.

    I'll ask you some of the questions you've mentioned.

    1. What is appropriate for pull-down resistance values in LDOA1, LDOA2, and LDOA3?

    2. I don't understand what the following is saying: It's like a personal English reading problem. Is it a little easy to explain?

    ->Cut LDO3P3 from the LDO3P3 plane, connect it to an output capacitor, supply the plane from an external supply

    Thank you.

    3. According to the comments that responded to the checklist Excel, Is the target you said "Would prefer on same layer" to be IC and Input cap right?

  • Hi Geonwoo,

    Sorry for the delay.

    1. My recommendation was 50 mA, so I guess ~36 Ω, 24 Ω, and 24 Ω respectively for LDOA1/2/3.

    2. Sure, let me try to re-explain in graphic form. Basically the goal is to disconnect the LDO3P3 from the large plane. This can be done by either using a small knife to cut the metal or using a small drill to remove the via:

    It's not easy, but I'm not sure how else to rule out LDO3P3 issue. However, LDO3P3 output cannot be floating, it needs a capacitor too, so you would also need to try to fit a capacitor there. My first thought is scraping away a bit of the GND solder and putting a cap vertically there and then running a small wire to the floating LDO3P3:

    3. Yes, input capacitors are the first priority - when they are far from the PMIC, it causes excessive voltage ringing on the input pins which can be a problem.

  • Hi,

    Thank you for your sincerity. I'm going to apply the things you said when i make pcb revision. I don't know when, but I'll conclude provisionally that there was a problem with the pcb artwork and conclude the question. If the problem improves after pcb revision, I'll comment separately for others to see.

    Thank you very much for your response so far.

  • Thank you for efforts here Geonwoo. Please feel free to provide the updated layout for review when completed.