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UCC5390: Gate driver's output gets clamped on +VCC2

Part Number: UCC5390

Dear all,

I have designed a SiC-based three-phase 3-Level T-type NPC voltage source inverter for a motor drive application.

I am using the UCC5390 gate driver by TI to drive the MOSFETs.

The converter switches normaly at a switching frequency of 500Hz.

 In frequencies higher than 25kHz the gate drivers' output voltage gets clamped on +VCC2 while the input is a pwm signal.

The result is shorting the phase.

I attach the figure.

Is it a known issue? Is the gate driver not rated for high frequency operation?

Thanks in advance. I am looking forward to hearing from you.

Best regards,

Giorgo

  • Hi Giorgio,

    The switching frequency capabilities of the gate driver would depend on the power dissipation which is also dependent of the driving voltage and loading conditions.

    • Which variant of the UCC5390 are you using?
    • Would you be able to share a schematic of the gate driver portion with component and power supply values?

    Best regards,

    Andy Robles

  • Hi Andy,

    I am using UCC5390S, the 10A/10A split output configuration.

    I attach two screenshots of the schematic. I have used two configurations and have the same problem.

    The values of Vcc1 = 5V, Vcc2 = +15V, Vee2 = 3.3V. The voltage of the input pulses can be arbitrarily chosen to be 2.5V, 3.3V and 5V.

    Best regards,

    Giorgo

  • Hi, Giorgo,

    Can you verify you input PWM signal is correct?

    It may be the MOSFET you are driving is too large to switch at this frequency. As Andy mentioned, you may be exceeding the power dissipation capability of our device due to a heavy capacitive load at high switching frequency. Please see section 11.2.2.3 Estimate Gate-Driver Power Loss and 11.2.2.4 of the datasheet to verify your conditions are within the specifications of our device.

  • Hi Don,

    Thank you for your reply.

    I am trying to switch two SiC MOSFEts at 25kW. The models of the MOSFETs are C2M0080120D (http://www.farnell.com/datasheets/2047787.pdf) and C3M0065090D (https://docs.rs-online.com/3a4d/0900766b8149fd4d.pdf). They should be able to switch at several hundreds of kHz.

    The input signals can be seen in the original post. The first figure is the gate-source voltage of the MOSFET. The second is the voltage between pin-6 and pin-08 of the gate driver. The third figure is the PWM. While the PWM switches the Vgs stays the same.

    I have been measuring the case temperature of the gate driver using an infrared camera and it is lower than 40oC. The calculations regarding the heat dissipation wield Pgdq = 1.0281W and Pgsw = 22.5mW. The junction temperature is calculated at 44.226 oC. The results are overrated due to not being able to measure Icc1 and Icc2, so I take in account the current supplied to some differential amplifiers and their power supplies.

    So, the conditions are within the specifications of the device.

    I hope I have provided you with sufficient data.

    Are there any isolated gate drivers with the same configuration that you would recommend for switching SiC MOSFETs?

    Thanks in advance. I am looking forward to hearing from you.

    Best regards,

    Giorgo Kapino

  • Hi, Giorgo,

    Thanks for the clarification, this is helpful.

    Since you are using split outputs, you don't need D21. Can you try shorting it out and see if that resolves your issue?

    What is the value of R65? What is the purpose of C123, 124, and 125?

  • Hi Don,

    Thank you for your reply.

    D21 is used to change the turn-on and turn-off Rg. In one of the configurations Pin-6 and Pin-7 are shorted, so D21 defines Rg-on and Rg-off.

    R65 is 47kOhms. C123, C124 and C125 are decoupling capacitors. They are placed very close to the gate and source pins. The gate driver design is based in Cree's recommended gate driver for the SiC MOSFETs.

    I have observed that by reducing the Vcc1 voltage, the gate driver switches correctly at 25kHz. I will do more testing at 50 and 100kHz.

    Thanks in advance. I am looking forward to hearing frrom you.

    Best regards,

    Giorgo

  • Hi, Giorgio,

    The OUTL can only pull low, and the OUTH can only pull high. By placing D21, you are effectively incapacitating the OUTH signal as D21 will always be reverse-biased.

  • Hi Don,

    I have made some changes to the layout. The layout now is as can be seen below.

    I have reduced the value of Vcc1 to 3V. The input pulses voltage is 5V. Now I observe correct Vgs voltage at 25kHz.

    Best regards,

    Giorgo

  • Hi, Giorgo,

    Thanks for making the schematic change.

    If I understand your second paragraph correctly, you have VCC1 tied to 3V, and are driving the INx pins with 5V PWM. This violates the Absolute Maximum Ratings of our IC and is not allowed. You either need to change VCC1 to 5V, or reduce the amplitude of your PWM input signal.

  • Hi Don,

    I know and I am surprised but the only case that the gate drivers operate as they should is when Vcc1=3V and INx=5V.

    When they are operated with a Vcc1 > 5V and a INx voltage of 5V, 3.3V or 2.5V, the clamping, that is shown in my original post, occurs.

    Is that a known issue?

    Also, are there any newer gate driver with the same package and configuration that TI would recommend for driving SiC MOSFEts?

    Thankls in advance. I am looking forward to hearing from you.

    Best regards,

    Giorgo

  • Hi, Giorgo,

    I suspect an issue with the decoupling on your VCC1 supply. It may be dropping below the UVLO threshold momentarily and causing an issue.

    Also, keep in mind the logic thresholds for this device. It has "CMOS-compatible" inputs which mean the input thresholds are a percentage of VCC1, so when you change VCC1, the logic threshold changes.

    This part is fine for driving Cree's SiC mosfets. In fact, they are using a part from this family in their reference designs.

  • Hi Don,

    Thank you for your quick reply.

    A ceramic 100nF capacitor is used for capacitive decoupling. The Vcc1 input is supplied by a power supply and it is constant.

    In each test Vcc1 is constant and INx is also constant. The power supply usualy shows 5V and 20mA for all 12 gate drivers. In each test, INx is exclusively either 2.5V, 3.3V or 5V. I have tried with different  values because the clamping occured.

    Do you have any suggestions regarding that?

    Thanks in advance. I am looking forward to hearing from you.

    Best regards,

    Giorgo

  • Hi, Giorgio,

    since a high input is only understood when the logic input voltage is > 0.7*vcc1, you should be in using 5V logic if you have vcc1 at 5V. 

  • Hi Don,

    I understand your argument but when I am using a 5V logic signal with VCC1 at 5V, the Vgs voltage is getting clamped as it can be seen on the first figure.

    On the other hand, when the logic signal is 5V with a VCC1 at 3V or 4V, the Vgs voltage is correct.

    I will try to attach figures on a different comment.

    I will do some EMI testing to make sure that the layout is not the problem and get back to you.

    Best regards,

    Giorgo

  • Hi, Giorgo,

    Do you have some kind of resistive load on the input circuitry which is dragging it down? In your original post, the PWM isn't getting up to 5V.

  • Hi Don,

    No there is no resistive load.I am using an FPGA and the output is controllable. The output can be set to 2.5V, 3.3V and 5V, so I was testing to see if I can get rid of the clamping.

    Best regards,

    Giorgo

  • Hi, Giorgo,

    There is something odd going on here. You must adhere to the specifications in the datasheet for our part to work correctly, and to ensure reliability.

  • Hi Don,

    Thank you for your reply.

    In the figure to the left, the Vgs output of the gate driver can be seen with the VCC1 and PWM signals' amplitude of 5V. It is the complimentary transistor of the original figure. The specifications of the datasheet were followed. It can be observed that one of the transistors is getting clamped to +VCC2 and the other one is getting clamped on -VEE2.

    Is there some explanation why this is happening? This malfunction has damaged two inverters and costed me 6 months of developing and debugging.

    After some trial and error, with a PWM signal of 5V and a VCC1 of 3V, the Vgs voltage to the left was achieved. The signal integrity is better but there are still false turn-ons or the gate driver doesn't turn-off when it should.

    Is there a solution to this problem? Is there another component that could be used?

    Thanks in advance. I am looking forward to hearing from you.

    Best regards,

    Giorgo

  • Hi, Giorgio,

    Using a PWM input signal of 5V when VCC1 is 3V violates the Absolute Maximum Ratings, and can not be allowed.

    Can you set your PWM input voltage and VCC1 within acceptable limits, insuring the "highs" are > 0.7*vcc1, and the "lows" are < 0.3*vcc1, and then make a plot of the PWM input signal directly at the chip, and the output, again directly at the chip? These obviously should match. Can you zoom in so we can see individual PWM cycles and not a super wide timebase like you've been doing?

    I think you are trying to run this at 500 kHz, right? That should be okay. If it doesn't work correctly at 500 kHz, please reduce the switching frequency until it does work, and let me know where that happens.

  • Hi Don,

    I have taken measurements using a smaller timebase. The VCC1 is 5V. The PWM is switching between 0V and 5V.

    The switching frequency is 100kHz. On the bottom axis the PWM signal can be seen. On the top the Vgs signals can be seen. The The Vgs does not follow the PWM.

    At higher duty cycle the waveforms look like the following:

    At zero crossings, where the duty cycle is smallthose waveforms can be observed:

    And I have also taken some extra measurements using a timescale of 20us/div:

    I still don't understand why this is happening.

    Best regards,

    Giorgo Kapino

  • Hi, Giorgio,

    I got tied up on some other tasks today, let me get back to you tomorrow. 

  • Hi, Giorgio,

    This is very strange. I can't explain why the output stops switching and stays HIGH for some time period before recovering.

    I worry maybe the chip is damaged from violating the Absolute Maximum Ratings for it. Have you swapped out the driver and seen the same behavior when driving everything under the Recommended Operating Conditions?

    In your 3L converter, is this occurring in the half bridges or the back-to-back switches? How are you powering your drivers?

  • Hi Don,

    In the beginning, I followed the datasheet specifications and still got the same waveforms.

    That is why I started the trial and error testing.

    I don't find it probable that all of them were damaged since the beginning.

    This is happening between the half-bridge switches and the auxiliary ones. 

    The VCC1 is supplied by an external power supply, the PWM signals are provided from dSPACE MicrolabBox and VCC2 is provided by an isolated power supply 12V -> +15V/-3V.

    Thanks in advance. I am looking forward to hearing from you.

    Best regards,

    Giorgo

  • Hi, Giorgio,

    let me confer with my colleagues and get back to you next week. 

    best regards,

    Don

  • Hi, Giorgio,

    OK, we discussed this issue internally, and this is our feedback:

    1. Did you short out D21 in these measurements?

    2. We think the input PWM signals aren't accurately getting to our device. Ch1 turn off doesn’t follow Ch5, there is a fixed delay. So, we think maybe your PWM signals aren't getting to the inputs of our chip correctly.

    It is also interesting how your signal goes away, and then comes back later. It looks like this might be happening at the peak of your motor current waveform? Maybe ground bounce is coupling into the inputs, causing them to not receive the correct signal?

    Is there someone at your university who can put a second set of eyes on this locally? 

  • Hi Don,

    Thank you for your reply.

    We will take a look and let you know.

    Best regards,

    Giorgo Kapino

  • Thanks, Giorgo.