LMG1210: EMI/EMC couplings from "BST"-Pin to "PWM"-Pin during dead time in a Buck converter

Hi Stefan,

Welcome to the forum. Could you please label each signal in the images to know which signal is which?

Best regards,

Leslie

Hi Leslie,

thank you very much.

Unfortunetly I am not able to insert images here. In my first post I just clicked and droped it in the text box, which worked. Now I cannot choose or select the URL to post the signals/images here.

The signals/images above are:

( 1: PWM/LI                                        -                 2: LO Low Output )

( 3: HO High Output                           -                 4: Vds Q1 )

( 5: Vds Q2                                         -                 6: BST )

Please let me know if I can help any further.

Kind regards

Stefan

Hi Leslie,

thank you for your advices.

Increasing the VCC-VSS capacitors didnt change the signals. After I replaced the gate resistors to 2 Ohm, the trouble got decreased. But without any load, my application takes around 150 mA (typically is 50 mA to 60 mA). Also, without any load, the FETs Q1 and Q2 heating up to 60 ° C.

In my Layout I orientated on EPC9098. I think the switching path is making troubles in my driver path (EMI).

What do you think about the Bootstrap diode ? The bst pin looks like having big di/dt. Could that may be because of a bad diode selecting ?

Right now I am ordering another PCB, where the driver is more decoupled with the load path.

Kind regards

Stefan

Hi Stefan, 

At the beginning of this thread you mentioned that "VIN" is set to 30V. I assumed you were referring to the "VIN" net name, and not the "VIN" pin in the LMG1210 device. Based on your schematic, seems like you are bypassing the internal LDO and just supplying 5V directly on VIN pin and VCC pin. Please let me know if my understanding is incorrect. The reason I bring this up is because VIN pin can only operate up to 18V, not 30V.

Regarding the bootstrap diode and the other components in the bootstrap circuit, please refer to this apps note with details on the selection of each component as well as layout recommendations for this circuit: https://www.ti.com/lit/an/slua887/slua887.pdf?ts=1618343980910&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards,

Leslie

Hi Leslie,

please apologize the confusion. The power path is named "VIN" which is not connected with the "VIN" pin from the driver. The "VIN" pin is connected to 5V.

About my mentioned problem: It seems like, the problem occurs during the switching of Q2. Have you any experiences with a case like this? I think I may induce a voltage from my power path in the driver. I am currently making a layout, where driver paths and power paths are decoupled.

Kind regards

Stefan

Hello Stefan,

Our expert on this part, Leslie, is out of the office at the moment. She will respond to address your question shortly.

Regards,

Hi Stefan, 

Thanks for clarifying the voltage level on VIN. 

Could you please capture the waveforms below to find out where the noise is coming from? Please capture all signals listed on each bullet on a single plot so we are able to observed each of these at the same time when the noise / issue occurs:

• Scopeshot of LO-GND, HO-HS, HS-GND, HB-HS (please capture 1 with the timing scale you had before and a 2nd plot more zoomed in to the noise)
• Scopeshot of VDD, PWM, HO-HS, LO-GND to see if VCC has any noise

And I'd like to understand if you are probing these signals directly at the driver pins, specifically for HO and LO, or if you are probing these at the gate of the FETs.  

Best regards,

Leslie

Hi Leslie,

in this situation I measured the signals and plotted them in MATLAB.

LO-GND , HO-HS , HS - GND , HB - GND:

PWM(LI) - GND , LO - GND , HO - HS , (About VDD - GND I will send you next week another plot. I can only say, that it also has bouncing through the bouncing GND):

In my opinion, GND itself is bouncing way too much caused by the HS - GND switching. About my measurement methods, I am using spring clips to measure short distances between the signals. On the backside of the board, I have testpoints, which are close to gate resistors.

Please let me know if you have further questions or need more/precise plots.

Kind regards

Stefan

Hi Stefan, 

Thanks for the information, I'll look into the plots and get back to you. Are the LO and HO test points you mentioned located at the the driver HO / LO pins side of the gate resistor, or on the FET gate side? It's important for us to understand if you are measuring close to the driver pins or close to the gate of the FET. 

Regards,

Leslie

Hi Leslie,

the test points LO and HO are located at the output of the gate resistors (R2 and R4). VIN, HS and GND test points are close to the FETs.

Kind regards

Stefan

Hi Stefan, 

Thank you. I'll look into these plots and get back to you on Monday. Please share the scope shot with VDD included once you have it. 

Best regards,

Leslie

Hi Leslie,

as promised, the scope shots with VDD to GND:

I have already three PCB's with the LMG1210, unfortunetly no one does work properly. The gate path (Q1) in two of my three layouts look like this:

1)

2) 

@Mamadou I will try to work with the PWM resistor and capacitor. I will let you know if that helped.

I don't really want to increase the Cgs capacitance or using a high gate resistor. than 2 Ohms. The reason why I choosed GaNFETs is to do fast switching and decreasing losses. With the LMG1205, I had no bouncing problems.

Kind regards

Stefan

Hi Stefan,

Few points from your latest waveforms.

1. During the rising edge of the HO_HS, there appears to significant ringing on the supply which likely points to either insufficient filtering on the bias. The second possibility more likely based on your 2nd and 3rd waveforms is shoot-through event where both HO and LO are high. On both the waveforms, LO and HO appears to both be high simultaneously.

It seems that LO has a certain delay before responding to LI low commands which intersects with the HO low to high transitions. Can you confirm your dead time and actual prop delay measured? From the plots, it looks like the prop delay is >=35ns, can you confirm?

2. The Cgs capacitance and gate resistors will help slow the dv/dt and will help us understand whether there is any improvement while we figure out the root cause of the issue. I assume while you have been collecting the latest waveforms that VDD has the previous capacitance values that Leslie previously recommended.

3. The gate drive loop appears fairly small though we want to confirm that VDD caps are directly across the IC VDD/VIN pins.

Regards,

-Mamadou 

Hi Mamadou,

1) The surface of the switching node is huge, which makes the the HO - SW signal increasing during its on time.

The dead time is 15,5 ns due to 33kOhm resistors (R1 and R3). I can measure the dead-time at the Drain-Source, which gives me around 15 ns. When I measure between LI falling and LO rising, I can measure a time of 33 ns:

2) The VDD input capacitors are 10 uF and 100 nF for high frequency filtering. In my opinion, the VDD voltage is ringing because of the ground bouncing and not because of a pulse current. Here are two different Layouts with different placings:

Thanks for your patient. Kind regards

Stefan

Hi, Stefan,

Mamadou will get back with you tomorrow. 

Hi Mamadou,

here are the signals you asked (LO high, HO low) with a dead time of 20 ns:

For my next Layout I can change the position of the VDD caps as you mentioned.

Changing the C38 results a better behaviour of the PWM signal:

I further increased the gate resistance to 2 Ohms, which results to way better signals compared to the last measurements.

As you said, dv/dt or di/dt of the switching is may the cause for the trouble. In the last layouts I orientated myself on TI's HVP012A.

Kind regards

Stefan

Hi Mamadou,

I sent you a friend request to show you some images of my layout. Please accept.

Kind regards

Stefan