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[FAQ] TPS546D24A: When I scan my I2C bus, I noticed the TPS546D24A responds to multiple I2C addresses. What addresses and why?

Part Number: TPS546D24A

I am working on a design that uses the TPS546D24A.  When I scan the I2C bus addresses on the system, I see the TPS546D24A is responding to multiple I2C address. 

What I2C addresses does the TPS5446D24A?

Why does the TPS546D24A respond to multiple addresses?

  • The TPS546D24A does respond to multiple I2C addresses by design.

    The TPS546D24A offers a PMBus® compatible digital communications interface and the SMBus defined Alert Response Address (ARA) which requires it to respond to transactions addresses to several I2C addresses.  Each is detailed below.

    1) Specific Device Address  (10h - 2Fh)

    The TPS546D24A will respond to transactions addresses to the specific device address assigned to the TPS546D24A via the resistors (default) on its ADRSEL pin or the value stored in NVM if the Address bit in PIN_DETECT_OVERRIDE is set to 0.

    2) I2C General Call Address (00h)

    The TPS546D24A will also respond to the I2C general call address (00h) 

    3) SMBus Alert Response Address (0Ch)

    The TPS546D24A will ACK I2C/SMBus transactions with an Address Byte of 0Ch (12d) if the TPS546D24A is asserting its ALERT# pin and will respond with its assigned device address (See number 1 above)  if the Read/Write bit is a READ.

    For more information about the TPS546D24A PIN_DETECT_OVERRIDE command, refer to the TPS546D24A product folder at 

    For more information about System Management Bus see the latest specifications at 

    SMBus reserved addresses are listed in Appendix C (Table 17 in SMBus Revision 3.1)

    For more information about Power Management Bus see the latest specifications at