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TLC6946: Trouble with the output to the TLC6946

Part Number: TLC6946

My circuit design is as follows:
I have 8 TLC6946 in a 1:4 MUX; a microcontroller which outputs data via two SPI's (Master SPI: Data, Slave SPI: LAT); and an FPGA which outputs the GLCK signal and the VSync signal.

My problem is the following:
When I output all the data, the FPGA sends the VSync signal after the current GCLK period. Sometimes pixels appear in the last described column of the TLC6946 when switching. I can't explain this problem, because I proceed exactly as the datasheet states.
Does anyone have an idea what this could be due to?

I would be very grateful to anyone here.
Best regards,
Michael