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TPS56C215EVM-762: Hiccup waiting time problem

Meng Liu
Intellectual 1765 points
Part Number: TPS56C215EVM-762

Hi support  team:

I am tested Hiccup status, in my understand if output current more than 13.8A, system well trigger hiccup mode so l had test this situation. the test waveform as follow.

 

In my test, hiccup wait time is 26.7ms? l don't know it reason?

in addition: why output rise time has 6ms?  the soft-start time just 1ms

  • +1
    TI__Expert 7500 points

    Hi Meng,

    Same as the other thread, what is the Css value of this setup? The hiccup enable delay is related to SS time which is 7 cycles of Tss. We need to double check the SS time. When measuring the SS time, the duration should be SW first switching pulse/Vout starting ramp up point to 0.9*Vout target value.

    As for your second question, TPS56C215EVM uses 0.047uF Css, so the calculated Tss should be 4.7ms. According to Figure 14 of the user guide, from Vout starting ramp up to 0.9*Vout (0.9*1.2V=1.08V), the SS time is about 4.7ms. Adding the last 10% time, the total rise time is about 6ms.

    Thanks,

    Lishuang