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BQ25121: Excess quiescent current draw beyond specification when enabling the LDO in some devices

NateEE
Prodigy 160 points

Part Number: BQ25121
Other Parts Discussed in Thread: BQ25120A, ,

I know this part is being deprecated and that BQ25120a should be used as a replacement where possible, but a first run of devices of our product shipped before the notice and replacement part became available. 

A couple devices in our first run came back to us with an issue of drawing too much power at all times, on the order of 100uA to 300uA. After investigation, we found that the current would disappear if we shut off the LDO powering just one sensor on the board (LS/LSO pin). We cut the trace and confirmed that the excess current draw persists (or gets even worse) when we turn on the LDO output and there is nothing connected to the output. 

It may be possible that this is a solder issue under the BGA but it's impossible for me to test that. Therefore I'd like to know if behavior like this has been observed before in the field or in the lab, and if my application might be doing anything to trigger the condition. Note that the majority of the devices in this product delivery don't exhibit this behavior and have quiescent currents in line with the datasheet specification, so this would have to either be a part to part variation or just that I've set something to a knife's edge of compatibility. The circuit is based off of the typical application circuit from the datasheet, but with a 10uF cap on PMID, no diode/connection between PMID and PG, and no battery monitoring. Both SYSOUT and the LDO are set to 3.3V in our application. 

It's important to me to have this answered because I need to know if this can also happen with the BQ25120a and if there's something I can to do prevent it. 

Regards, Nate

  • 0
    TI__Genius 12485 points

    Nate,

    I haven’t seen this mode before.

    Since you do mention a couple devices are failing, the probability of a bad solder job is marginal given that all the devices are failing the same way.

    Have you tried a different unit on a “bad” board? What is the voltage range of the sensor connected on LDO?

    I am curious if on powerup, you are turning on the LS mode before turning it into LDO. Note that LS will have a voltage as high as VIN when turned ON.

    Is the 300uA measured from VBAT?

    Also I am releasing the BQ25121A this May. This might offer some relief for our BQ25121 customers.

    Regards,
    Gautham Ramachandran
    Battery Charger Applications

  • 0 in reply to Gautham
    Prodigy 160 points

    Gautham, thanks for responding. 

    The connected sensor is an ultra low power accelerometer. On one of the boards we used a heat gun to completely remove the sensor from the board and verified the extra current draw was still there. There is nothing else connected to the LDO output on that board spare the output capacitor. 

    We are not turning on into LS mode, we keep the LDO output voltage at 3.3V. The 300uA extra current draw is measured at VBAT, confirmed. 

    In the meantime I've conducted a lot more experiments to try and get you more information. We discovered that hitting the battery charger chip with freeze spray decreases the current consumption almost instantly, and it rises back up as it warms up. Hitting it with extra heat from a heat gun increases the current slightly, but not by much. 

    Once our sensor was removed from the board we discovered that the current draw is quite dependent on the output voltage setting of the LDO. Decreasing the LDO voltage from 3.3V to 3.0V drops the excess current consumption to one fifth of the original value. A value of 2.5V on the LDO makes it so the extra current consumption is gone completely. VSYS remained at 3.3V throughout this test. 

    Although it's good news that there will be a BQ25121A part in the future, unfortunately I'm expecting my next production order to get shipped out in May, so it won't come in time for the next batch. I think we can use the BQ25120A in the meantime with a small firmware change, which I'm busy confirming is the case. 

    Regards, Nate

  • 0 in reply to NateEE
    TI__Genius 12485 points

    Nate,

    What is the battery voltage when you do this test? I am wondering if we are running out of headroom for the VSYS to operate. 

    Can you lower the VSYS to 2.5V and see if the 300uA is still present?

    regards,

    gautham

  • 0 in reply to Gautham
    Prodigy 160 points
    Gautham,

    For convenience, we're temporarily running the boards off of a power supply at 3.9V, but it behaves the same when we connect a normal LIPO on the input. I've seen the current consumption of the board increase when the battery voltage drops to 3.45V on other boards in the past, and so I decrease VSYS when putting the device into its low battery sleep state to avoid problems.

    Do you want me to try decreasing both VSYS and VLDO to 2.5V together, or just VSYS to 2.5V while leaving VLDO at 3.3V? I suppose I'll try both and get back to you when I've completed the experiment.

    Regards, Nate
  • 0 in reply to NateEE
    TI__Genius 12485 points
    Nate,

    the common mode headroom with a safe limit is around 600mV + VSYS setting for VBAT to be. I would recommend to just move VSYS alone. VLDO should be okay.

    thanks,
    gautham
  • 0 in reply to NateEE
    Prodigy 160 points

    It turns out "board 2" I previously measured at 100uA extra draw was actually running in the wrong mode the first time around (I've been using the "board 1" 300uA extra draw board mostly until now). Now that I have "board 2" running in the correct mode it draws 500uA extra. Go figure.

    Anyway, here's the results from the test you asked for, as total current drawn from the battery:

    Battery voltage at all settings: 3.9V
    VSYS 3.3V and VLDO 3.3V: 588uA
    VSYS 3.3V and VLDO 2.5V: 50uA
    VSYS 2.5V and VLDO 3.3V: 235uA
    VSYS 2.5V and VLDO 2.5V: 190uA

    Remember that nothing aside from a capacitor is connected to the output of VLDO while taking these measurements.

    Regards, Nate

  • 0 in reply to NateEE
    TI__Genius 12485 points

    Nate,

    This doesn't add up at all. I will send you an email (i have your info) I would need schematics to check. 

    regards,

    Gautham

  • 0 in reply to Gautham
    Prodigy 160 points

    For anyone following the thread, Gautham and I had some email correspondence back and forth after the last post, so I'll update the post one last time with the problem explained and our resolution.

    When we designed the board we didn't realize that internally the VINLS pin directly powers the LDO circuitry. We simply followed the (incorrect) datasheet advice that if VSYS is greater than VLDO then connect VINLS to VSYS, or if VSYS is less than VLDO then connect VINLS to PMID. There was no advice for if VSYS was exactly equal to VLDO on what to connect VINLS to, so we assumed it didn't matter and connected VINLS to VSYS, while setting both VSYS and VLDO to 3.3V. It turns out that on some devices the LDO would draw excess quiescent current if a voltage input headroom of at least 400mV was not provided, in other words it was only safe to run the LDO if the voltage on VINLS was at least 400mV greater than the output setting of VLDO. For practical designs, I'd recommend using 500mV or 600mV headroom personally. Gautham said he'd be updating the datasheet to make that section clearer, but I'm unsure of the exact language that will be used at this time. This problem will affect your ability to run in LDO mode off of a LIPO battery, as you need to maintain at least 600mV headroom with the lowest battery voltage you will operate at while draining the battery. Don't try to set the LDO to 3.3V while running on a LIPO.

    Note that the exact amount of increased quiescent current draw in this condition may vary wildly between boards, anywhere from a couple tens of microamps to several hundred microamps, which can make the problem difficult to catch and debug.

    For our design it turns out that because there was no headroom the LDO wasn't actually providing any meaningful regulation anyway. We set the LDO output voltage to 3.4V to switch the LS/LDO output pin over to load switch mode, which solved the quiescent current problem. We still get 3.3V on the LS/LDO pin because VINLS is connected to VSYS, and our VSYS is set to 3.3V output. There's probably a bit more noise on the line than we'd like, but after testing it seems that our particular design doesn't actually care that much, so we got a bit lucky in that regard.