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UCD9244 + UCD74120 switching frequency problem

xiao peng ma
Intellectual 640 points
Other Parts Discussed in Thread: UCD9244, UCD74120

I use these two chips to generate a freescale T2080 VDD power.

Input voltage is 12V and ouput voltage is 1.025V.

When the switching frequency is above 1000khz,sometimes there will be no ouput voltage and FLT bit will be set in GUI.

It is all right when the switching frequency is below 1000khz.

Why?

Here is my schematic and project file.

I only change the switching frequency to 1100khz and there will be some failure.

UCD9244_Power.rar

  • 0
    TI__Intellectual 2270 points
    Hi Xiao Peng Ma,

    UCD74120 FLT Pin is assert because of : Output over-current/High-side Fault/UVLO/Thermal.
    Based on your describe, it may trigger Output over-current fault at the power up stage, as the switching freq increase while the DRIVER_MIN_PULSE remain the same.

    Suggested you could check the output current at SW node at the power up transient, to see whether it exceed 50A high-side current limit.
    Or test the output voltage at the VDD node, to check whether it produce a voltage surge at the moment of power up.

    If it is Output over-current fault, you could try to decrease the switching freq or enlarge the DRIVER_MIN_PULSE if above 1000KHz is needed.
  • 0 in reply to Fery Feng
    Intellectual 640 points

    Thanks.

    When the failure occurs,I probe the FLT signal,its level is low,that confuse me.

    Howeve I will try what you have suggested.

    In Addition,I find that the current displayed in GUI may be larger than the actual value.

    When the 12V power supply is 1.7A, the current displayed in GUI is 4A.

    When the 12V power supply is 2.4A, the current displayed in GUI is 23A.

  • 0 in reply to xiao peng ma
    TI__Intellectual 2270 points
    Hi Xiaopeng Ma,

    I reviewed your configuration and found you set the over-current response as"Shut down immediately" and "No Restart".
    So once the over-current occurs, FLT assert and turn both high-side and low-side gate driver low, and then the over-current fault disappear, then FLT de-assert at the falling edge of a subsequent PWM pulse.
    You may view this process if you monitor the FLT Pin by oscilloscope.

    For the different between actual current and the current GUI shows, you need to modify the "IOUT_CAL_GAIN" and "IOUT_CAL_OFFSET" to a suitable value based on your hardware circuit.
  • 0 in reply to Fery Feng
    Intellectual 640 points

    Thanks 

    How can I calculate those values?

    I think that they should be calculated by the GUI automatically?

  • 0 in reply to xiao peng ma
    TI__Intellectual 2270 points
    Hi Xiaopeng Ma,

    "IOUT_CAL_GAIN" and "IOUT_CAL_OFFSET" , these two value configured in GUI is choose based on your hardware circuit, so they need to modify manually.

    Equation shows below, only if the hardware circuit is set as datasheet recommanded:
    IOUT_CAL_GAIN = 47*DCR
    IOUT_CAL_OFFSET = 0.5/IOUT_CAL_GAIN