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UCD3138: Using cycle by cycle current limit with ACOMP and set to falling trigger

Part Number: UCD3138

Hi all,

 - I'm using bi-direction hall sensor for current sense. (When current = 0A, hall sensor output = 0.8V)

 - Can I set cycle by cycle current limit when current is negative, which is, when hall sensor output goes form 0.8V and below?

 - I'm using ACOMP_D and want to do CBC current limit when hall sensor output drop below 0.25V.

  FaultMuxRegs.ACOMPCTRL1.bit.ACOMP_D_SEL = 0;      // THRESH
  FaultMuxRegs.ACOMPCTRL1.bit.ACOMP_D_THRESH = 20;  // 0.25V
  FaultMuxRegs.ACOMPCTRL1.bit.ACOMP_D_POL = 0;      // Falling
  FaultMuxRegs.DPWM1CLIM.bit.ACOMP_D_EN = 1;

 - When I removed the code above, the DPWM outputs PWM for gate drive normally. However, when I enable the code above, DPWM outputs nothing.

Please help! Thank you!

  • Hello,

    An engineer is looking into this and will respond.
  • I believe that you should be able to do it, and the part of the code you sent me looks right, but it's not the whole story. I am always forgetting to set the ACOMP_EN bit, the global one, not the one for the individual comparators. And there are the other bits in the fault mux and the DPWM that need to be set as well to enable it all the way through. You may need blanking, if the current is going high (more negative) on the end of the period. With the internal delay, that will extend into the beginning of the next period and kill the next pulse before it gets started.

    To check that things are working, I often have to do kind of a test bench where I can put in a controlled voltage and follow things through the FAULTMUXRAWSTAT, and so on. Sometimes I will use another DPWM feeding into the comparator and change its timing to see how it affects the desired DPWM. With the high level of configuration possible on the UCD, sometimes you have to debug it more like an analog circuit and try to see how the digital signal is progressing through the system, including injecting a signal at the start.