Hi Support team champs:
My customer is having a question regarding adding a DC offset on CT to avoid the DCM ringing and noise. Suppose a DC offset is added on CS pin and PWM ramp, the current signal seen by the controller will always larger than the actual inductor current signal (say actual current signa + 120mV offset + PWM ramp).
Do we need to adjust the Rs value or the peak current limit threshold in order to compensate this offset? Otherwise the peak current level will always smaller than what it should be.
Also Why does add the PWM ramp can help to increase the signal noise immunity? Also what does this paragraph mean?
"To counter for the offset (VOFF) just requires adjusting resistors ROA and ROB to ensure that when the unit goes
discontinuous the current sense resistor is not seeing a positive current when it should be zero."
The offset is always there which the CS pin can always seen a positive current, how's adding ROA and ROB helps the controller not seeing this positive voltage?
Thank you.
Best Regards,
Wei-Hao