Dear Sir,
We are using TPS54821RHLR for generating 1.03V from 5V input, the circuit designed as per webench attached the simulation report for 8Amps requirement,
Actual board Scenario
In our design we are facing a voltage dip which generates pgood (interfaced to enable of next regulator) and shuts down the next power cycle regulator.
The voltage is dropped to 916mV (actual voltage 1.03V) which is provided to Arria10 SoC expected to take less then 5Amps,
Independent load test Scenario
To test the voltage drop we have isolated the SoC and provided with resistive load (0.2E) at the load capacitor. We observed dip in voltage 952mV. we need to nullify the voltage dip when load is applied, kindly suggest what needs to be taken care to minimize/completely eliminate the voltage dip.
Please note that Total load capacitor is 100uF x 2 at regulator and additional 100uF near SoC.
In our PCB we will not be able to add additional bulk capacitors. To reduce the voltage dip during dynamic load which are the other components which could be varied.
Kindly let us know is there any web simulation to analysis of dynamic load test for the same.
Schematics:
CRO Snap shot of the Voltage Dip:
WEBENCH Schematics with Report:
Best regards,
Shashi.