Can someone please shed some light on this described phenomenon on the TPS54821?
Your data sheet claims:
“In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.”
Why is this not recommended? Does the device come out of regulation? How many clock cycles does this take to become coherent again?
