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TPS53632G: How to use it

user5015634
Intellectual 260 points
Part Number: TPS53632G
Other Parts Discussed in Thread: TPS53632

Hi!

I have a question about  using TPS53632G. If the TPS53632G is used with controlling a half-bridge conveter ,what is the  max Vout of the conveter ? In addition,the TPS53632G is only used in the POL conveter and the max output of the conveter is 1.52V?

what is the different between the TPS53632G and TPS53632?

  • 0
    TI__Mastermind 18685 points
    The max output voltage depends on the topology/power stage.
    For the half-bridge current doubler topology, the max Vout= Vin(min)/(4*Nps) where Nps is the transformer primary-to-secondary turns ratio.
    For example, 5:1 turns ratio, Vinmin=42V, Vout is 0.5~2.1V. You can use resistor divider to extend the Vout beyond 1.52V.

    TPS53632G and TPS53632 are from the same DCAP+ family with fast transient performance, but they target different applications. There are a lot of differences between them. TPS53632G is for half-bridge PWM controller optimized for GaN-based 48-V DC/DC converter.
  • 0 in reply to Tiger Zhou
    Intellectual 260 points
    Thanks for your answer. In the example,what is the mean of the“4”in the denominator ?And, is it ok that the TPS53632G is used in a half-bridge topology with full wave Rectifier in the secondary ?(VIN=36-75VDC,VOUT=28V,f=1M). If it can be used , now, how about the two outputs of PWMS ,they are in the same phase or output difference 180 degrees? AND what's the reason about it can not be usde in the above? The last question,what is the max duty ratio of the chip ?
  • 0 in reply to user5015634
    TI__Mastermind 18685 points
    The "4" was derived from 1/2 Vdc with 50% duty. You can use it with full-wave secondary rectifier. The two PWM outputs are 180 out of phase. Although the chip is limited by minimum on time and minimum off-time, both are 20ns, the duty cycle is less than 50% in a two-phase configuration. TI has a free tool to help you with your design, it is called "power stage designer" (TM). You can download from ti.com.
  • 0 in reply to Tiger Zhou
    Intellectual 260 points
    OK ! Thank you very much for your support，your answers solve my question！Very good! Now I will buy it for my design! Thank you !
  • 0 in reply to Tiger Zhou
    Intellectual 260 points

    Hi ! I'm using TPS53632G to design a half-bridge converter. The parameters: VIN=36-75V, VO=28V, IO=10A. I 'd like to ask you a few questions about the data sheet（Revision A ） during the design process.

    1、7.4.1 and 7.5.7 on the discussion of single and multip phase, how to understand the problem of multip phase? Which pin is CSP3?

    During single-phase operation, every SW_CLK signal generates a switching pulse on the same phase. Also, ISUM
    voltage corresponds to a single-phase inductor current only.
    During multi-phase operation, the controller distributes the SW_CLK signal to each of the phases in a cycle.
    Using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives
    the required interleaving of 360/n, where n is the number of phases.——7.4.1

    7.5.7 Active Phases
    Normally, the controller is configured to operate in 3-phase mode. To enable 2-phase mode, tie the CSP3 pin to
    a 3.3-V supply and the CSN3 pin to GND. To enable 1-phase mode, tie the CSP2 and CSP3 pins to a 3.3-V
    supply and tie the CSN2 and CSN3 pins to GND.——7.5.7

    2 Overvoltage Protection

    In7.3.7，7.3.7 Overvoltage Protection
    An OVP condition is detected when the output voltage is greater than the PGDH voltage, and greater than VDAC.
    VOUT > + VPGDH greater than VDAC. In this case, the converter sets PGOOD inactive, and turns ON the drive for
    the low-side MOSFET. The converter remains in this state until the device is reset by cycling the V5A, VDD or
    VINTF pin. However, the OVP threshold is blanked much of the time. In order to provide protection to the
    processor 100% of the time, there is a second OVP level fixed at VOVPH which is always active. If the fixed OVP
    condition is detected, the PGOOD are forced inactive and the low-side MOSFETs are tuned ON. The converter
    remains in this state until the V5A, VDD or VINTF pin is reset.——7.3.7

    What do the VPGDH and VOVPH mentioned in the article refer to? How does overvoltage protection detect and work?

    In the 6.5 Electrical characteristic:

    PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
    VOVPH Fixed OVP voltage VCSN1 > VOVPH for 1 µs 1.60 1.70 1.80 V
    VPGDH PGOOD high threshold Measured at the VFB pin w/r/t VID code, device
    latches OFF    		 190 245 mV
    VPGDL PGOOD low threshold Measured at the VFB pin w/r/t VID code, device
    latches OFF    		 -348 -280

    How do you understand these parameters? Overvoltage protection is detected by CSN1 ? When CSN1's voltage is greater than 1.7 V(VOVPH voltage? ),the  Overvoltage protection occurred? If so, how can the current be detected in this design? Because the CSN1 pin is connected to VO, and VO = 28V, how should current detection be configured?

    3  CURRENT SENSING

    If resistor  sensing is used, is a small resistor directly connected behind the output filter inductor to be detected without NTC thermistors compensation?
    If the secondary uses full-wave rectifier, how should the current sampling be configured? How to use CSP1, CSN1 and CSP2, CSN2?

    4  In 8.2.1.2.7,EQUATION 14, what is the RLL?

    8.2.1.2.7 Step 7: Set the Load-Line Slope
    The load-line slope is set by resistor, RDROOP (between the DROOP pin and the COMP pin) and resistor RCOMP
    (between the COMP pin and the VREF pin). The gain of the DROOP amplifier (ADROOP) is calculated in
    Equation 14.