LM5109A: BLDC driver failure

Hello Shuli,

thank you for your interest in the LM5109A and considering TI half bridge drivers in your design. I am an applications engineer supporting this device and will work to help resolve your concerns.

I see you commented that this new design is based on a 70W motor drive that works as expected, and this is a 200W design. I assume several design details have changed, including using larger MOSFETs and the switch node dV/dt would increase due to the higher switching currents.

On the bootstrap diode MMBD4448 I see that the current rating looks OK with a 100 Ohm bootstrap series resistance, but with a 10 Ohm resistance a higher current rated diode such as the MUR120 may be a better choice.

Since this is a motor drive application, I assume there may be very long on times of the high side HO output. Refer to the datasheet page 11 for sizing the bootstrap capacitor based on Mosfet gate charge and IC quiescent current, for the longest expected HO on time.

The schottky diodes placed on the driver outputs from HO to HS, HO to HB, and LO to VDD, LO to GND need to have low Vf and be placed as close to the driver pins as possible to limit driver output overshoot and undershoot. Confirm that you have the diodes with adequate rating and close to the IC. We recommend 1A rated diodes.

I see on the scope plots on page 1 that HS and HB transition high very soon after LO falls. Can you confirm if the LO scope waveform was on the MOSFET VGS directly, or the driver pin. High dV/dt can cause the Mosfet Vgs to have a positive spike that does not appear on the driver output.

Since this is a 1A limited driver, can you experiment with various gate resistor values? Try lower values such as 2.2 Ohm which will limit the Vgs rise from the MOSFET miller charge during switching. Also try larger values such as 10 Ohm to see if reducing the MOSFET switching times helps the issue.

To get a better understanding of the operation, can you provide scope plots showing the HO output as well as the HS, HB and LO?

Regards,

Richard Herring

Hello Richard,

Attached please find plots of HO,HS,HB and LO. Also included plot of HO signal at driver side and MOSFET gate side. The plots where taken from failed circuit. The motor spin but you can hear "hiccups" in the commutation.

The circuit is exactly as shown in the schematic without any modification.

As you can see LO stay low and it is probably part of the failure symptom.

You can see undershoot at HO,HS,HB which is definitely out of spec.

Thanks,

Shuli

Waveform 2.docx

Hi Jeff,

Thank you for your reply.

- VDD bypass capacitor -2.2uF and 0.1uF (C59 and C1 for phase 1)

- I didn't check different gate resistor value. If it is critical then please let me know the signals of interest .

- 'waveform2(failed board)-page1': as I mention the plots where taken from failed circuit. The motor spin but you can hear "hiccups" in the commutation. Hence I believe: LO stay low and it is probably part of the failure symptom. As you can see in the first attachment '3PH BLDC failure' – pic2, which was taken from good circuit, LO is toggling as accepted. So it is looks like the issue related somehow to driver failure.

- You are correct regarding '3PH BLDC failure' - pic1. For some reason bootstrap highside supply becomes shorted for a few 100ns. I'll confirm that it happened when HO it asserted. Do you have any suggestion how it could happened ?

What about the undershoot of the driver outputs with respect to VSS. As can be seen in 'waveform2(failed board)-page1' there is undershoot of about -10V ?

Thanks,

Shuli

Hi Shuli,

Sorry for the late reply. Thanks BP101 for covering for me! BP is right, we could be overdriving the FET. Let me try to explain.

3PH BLDC failure-1 I see a long deadtime and bodydiode conduction from HS voltage after HO pulse shuts off I presume. This makes me want to see what HO is doing at the time of the pulse. With long LO deadtime, why not make HO deadtime similar?

On Waveform2 The negative ring on HO shouldn’t affect the driver since HO rides on HS and will follow HS during turn off. LM5109A half bridge driver’s high side drive output HO is constrained by its buffer biases HB and HS differential voltage rating at the pins. Since HO follows HS we need a differential reading of HO-HS during the failure showing the HO-HS voltage stays within -0.3V and within spec of the datasheet abs max table 6.1

HS negative ring on HO turn off may be sending the HB-HS rating out of spec by overcharging the bootstrap cap and also overdriving the FET. A HB-HS differential voltage reading can be done to see if this is happening.

any update with results from larger resistor values?

Thanks,

Hi Jeff and BP101,

I understand your point regarding HO drive excessive and I'm going to replace gate resistors to 33R. I'll update on the results.

Btw-I tested MOSFET case temperature with 4R87 and found delta of +11 degrees Celsius vs ambient temp. which is ok. I'll retest it with 33R.

Regarding deadtime: As you pointed picture-1 at 3PH BLDC shows 1uS DT from HS voltage after HO pulse shuts off. In the attached file Waveform 3, picture 2-3, you can see zoom in HO and LO signals and DT.

I didn't understand your suggestion. I thought it will be better to decrease 1uS DT between LO rising up to HO pulse shuts off (Picture 2), Do you think it should be longer ??

 In addition, I found that motor time constant vs PWM frequency. Motor L/R= 0.0163mH/0.102 Ohm = 160u.

Since time constant should be much longer than PWM period I've change motor frequency from 20KHz to 40KHz.

As you can see in the attached file Waveform 3, picture 1, the peak current reduce from ~10A@20KHz to ~4.4A@40KHz.

Following frequency update to 40KHz, we drive the motor and after long minutes the motor stop spinning. We found high current consumption on 12V power plane. The failures was three drivers burn out. The MOSFETs are ok. Obviously we can see improvement when driving the motor at 40KHz and I'm consider to work with even higher frequency.

As I wrote we are now replacing gate resistors to 33R.

Thanks for your support,

Shuli

Waveform 3.docx

Hi,

Good news. The motor is working few hours with no issue.

modifications:

• Rgate = 33R
• Freq = 40KHz
• DT = 400nS
• VDD = 10V
• Adding 220uF on Motor_Vin

Since adding 220uF and changing VDD to 10V is hard to implement in current design, I'll try to understand there necessity.

Any comment and suggestion are welcome.

Thanks again,

Shuli

HI Shuli,

Good to hear this news though above I was referring to finger on gate driver package for dissipation more than NFET though both are equally worth checking. IC package peak power dissipation graph can often help to maximize total Gate QG GtROn/Off values into safe operating range in forward Transconductance of NFET.

We discover just the opposite 12.5Khz was more efficient on NFET with 1.3KW steady motor load @138vdc. Infineon NFET total QG-98 from table graph (+15VB) and gate resistors - GtROn:(60R)/ GtROff: 1amp Schottky +(100R) worked nicely in parallel GtRon. Gate driver (another vendor) could source/sink 350ma/650ma for <10us pulses shorted to ground. So GtRoff = 8R57 parallel even though GtRoff 10R or (600R/70R = 8R57) GtRoff value. Product over the sum in that case to figure Gtoff value with Gton selection especially if (dv/dt) is very high Gton HO can be slowed via higher GtOn values at low NFET BVDss, say below 24vdc. GAN device are excellent in that regard and suffer no effects of body diode Trr, even Opti MOS3 can not touch that marvel.

Recall our RGate calculation roughly sinks/source 1.2A/850ma with no resulting issues of +15VDD boost switcher @1 amp peak. 20Khz the low side NFETS TjMax would quickly rise above 60*c and not so much at 12.5Khz with 500w AC generator load.