• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 64 subscribers
  • Views 729 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

UCC27524: Device not switching from 3.3V FPGA I/O Logic

UCC27524: Questions for UCC27524 Threshold at different VDD voltage

Jacky Wang(QD)
Genius 9940 points
Part Number: UCC27524
Other Parts Discussed in Thread: UCC27423

Hi Experts,

We have shown the enable threshold vs. temperature curve in the datasheet regarding to VDD=12V and VDD=4.5V, but customer wants to know what it is about on VDD=15V, can you kindly help to provide? Thanks a lot!

  • 0
    TI__Genius 12990 points

    Hi Jacky,

    Thanks for reaching out to us about this question. This spec is characterized across temperature to account for any variation. Since there is not an EN (or IN) threshold vs VDD voltage plot in the datasheet or in char test data we can assume that this spec does not have significant variation to be of concern. The EN threshold at any VDD voltage should be the same.

    Its important to note that across temperature the input has a negative temp coeff that can span from 230k at -40C to 130k at 140C. This pull up resistance variation will create variation of the voltage on this pin across temp, however it will stay constant across VDD voltage.

    Hope this answers your question, please let me know if you have any more!

    Thanks,

  • 0 in reply to Jeffrey Mueller
    TI__Genius 9940 points

    Hi Jeffrey,

    Thanks for the reply, but we are still confused about below two plots in the datasheet, I mean that at the same temperature like 0C and 50C, you can see the EN threshold is different at 12V VDD and 4.5V VDD, can you kindly help to explain about this? Thanks a lot!

     

  • 0 in reply to Jacky Wang(QD)
    TI__Guru**** 189399 points
    Jacky!!!!!!!!!!!!

    Lao peng you, how have you been?

    There seems to be a slight dependency on VDD as you've highlighted. Clearly, at VDD=15V, the thresholds will be shifted up. Let me have our colleague see what we can find on this.
  • 0 in reply to Don Dapkus
    TI__Genius 12990 points
    Hi Jacky,

    Thanks Don,

    Just wanted to update you guys on what I have found on this so far.

    As I understand it, the added leakage (for ex - 22.5uA at 4.5v and 60uA at 12v as far as 100ua at 20v AMR) is creating more current in the hysteresis circuit (This is assuming that there is a pullup to VDD from the hysteresis circuit making the slight dependency)

    This higher hysteresis current equals a higher potential difference on the comparator inputs which makes a higher voltage threshold as well as slightly higher hysteresis. I was unable to predict the EN thresh when VDD=15v however from what we know we can predict that 15v threshold will be very similar to 12v threshold or about 0.1v higher is so. This is apparent in figure 27 of UCC27423 datasheet.
    also, I believe the input threshold would have the same dependency of VDD toward the threshold.

    Hopefully our colleague mentioned in Dons post can further clear things up,
    thanks,
  • 0 in reply to Don Dapkus
    TI__Prodigy 40 points

    Hi Jacky,

    I ran a couple tests in the lab and found that for VDD= 15V the enable threshold will behave within the electrical characteristics and very similar to the Figure 10 in the datasheet.

    Thanks,

    Carissa

  • 0 in reply to Carissa
    TI__Genius 9940 points

    Hi Carissa,

    Thanks a lot for the comfirmation.

  • 0 in reply to Don Dapkus
    TI__Genius 9940 points
    Hey Don,
    Long time no see, I have been all right, Ha Ha~