• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 63 subscribers
  • Views 3760 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Multistage inverting charge pump on TPS65150

Damien B
Prodigy 20 points


I am working on the TPS65150 to create voltages to a TFT panel. I need to create 9.3V on the boost converter, +15V on the positive charge pump and -10V on the negative charge pump, knowing I have 5V Vin.

For the two positive voltages no problems. For the negative voltage the datasheet says (page 14) that the charge pump is a one stage charge pump then the max output is -Vsup - Vdiode. (Vsup is 9.3V here).

Then I need to implement a second stage on the negative charge pump because  reading the datasheet I think it implies it is possible.

There is an example of a two stage charge pump for the positive one on the page 21 of the datasheet (figure 21). It is a bit different than the negative, on this charge pump it is to have a voltage over 2*Vsup. But i think the same idea is applicable on the negative one

I have two questions:

  • first what is the purpose on C17 for this charge pump? Wouldn't C18 be enought to have more than 2*Vsup?(of course if there is only C18, D6 is to be taken out too)

  • I think the same circuit (with or without C17 depending on your answer) is applicable on the negative charge pump to have a voltage below -9.3V (to get my -10V). Am i right on that?

  • 0
    TI__Expert 8010 points

    Hello Damien,

    It seems that you are referring to an older version of this part, please refer to this d/s next time: http://www.ti.com/lit/ds/symlink/tps65150.pdf

    The maximum output voltage that one charge pump stage can regulate is VGH_MAX = VSUP + VS - VDROP. In your case this would roughly be
    VGH_MAX = 9.3 V + 9.3 V - 0.7 V = 17.9 V (VSUP = VS for VS <= 15 V). As you only want to have 15 V on VGH, you do not need a second charge pump stage. And that also means that D6, C18, D7 and C4 are not required anyway.

    The rules for the negative charge pump are a bit different regarding the maximum regulated output voltages.

    One stage can regulate up to VGL = -VSUP + VDROP ~ -9.3 V + 0.7 V = -8.6 V. This implies that you will need a second stage to regulate to -10 V.

    The figure below shows how to add another inverting charge pump to figure 17 (page 22): Components C3, C7, D2, D3 are the ones from the figure in the d/s and the green-marked are to add. For regulated output voltage you have to set the voltage divider as described in chapter 7.3.2.1.

    Thank you,

    Best Regards,

    Ilona

  • 0 in reply to Ilona
    Prodigy 20 points

    Thank you for your answer.

    Could you please explain to me how is this second stage working?

    SW and VGL are switching Vs and Vsup in opposite?

    What are the purpose of each added component?

    Thank you very much.

  • 0 in reply to Damien B
    TI__Expert 8010 points

    Hello Damien,

    The purpose of the second charge pump stage is to pull the cathode of diode D3 below GND so that the capacitor C3 can be charged to a lower voltage < -8.6 V. As this stage is driven by the switching node of the boost converter (SW), the output voltage (cathode node) of this inverting stage is ~ -VSUP + VDROP ~ -8.6 V. To make sure that the output voltage is regulated to its desired voltage, you have to set the resistors R1 and R2, which controls the current of the first stage to regulate at the correct value.
    Attached is a model file, that you can simulate with TINA (TI Circuit Simulator: http://www.ti.com/tool/tina-ti ).
    Maybe this will clear your understanding a little bit more.

        InverterDoublerBAT54S.pdfInverterDoublerBAT54S.TSC 

    Thank you,

    Best Regards,

    Ilona

  • 0 in reply to Ilona
    Prodigy 130 points

    Hello Ilona,

    I am working on the same schematic for the VGL signal configuration and the same configuration.At the start up, we get an overshoot on the VGL signal.

    Using your simulation schematic, this overshoot is present too. Do you know a way to cut off this overshoot?

    Thank you,

    Best regards,

    Sébastien

  • 0 in reply to Sebastien.M
    TI__Expert 8010 points

    Hello Sebastien,

    In the attached TINA- file the output capacitor was connected between the output voltage of the second stage and the output voltage of the first stage whereas the output capacitance was split via C4 and C2 which is the reason why it caused an overshoot.

    If you connect a capacitor on the second output stage against ground the overshoot shall disappear, see attached corrected TINA- File.

    Best Regards,

    Ilona

    InverterDoublerBAT54S_outputcapcorrection.TSC

  • 0 in reply to Ilona
    Prodigy 130 points

    Hello Ilona,

    we did the test with our schema and the overshoot disappeared but we get an undershoot to -11.3V. Next, the signal goes to the right value -10V.

    We use a 100nF capacitor on the DLY1 pin to set up a delay on the -10V voltage. Before reach the delay time, the Vout voltage reach -9.3V (Vsup is 9.3V). After reach the delay, we get the undershoot and the signal goes to the right voltage.


    Have you any idea to cut off this undershoot?


    Thank you,

    Best regards,

    Sébastien

  • 0 in reply to Sebastien.M
    TI__Expert 8010 points
    Hello Sebastien,

    Have you tried to increase the output capacitance?

    Best Regards,
    Ilona
  • 0 in reply to Ilona
    Prodigy 130 points

    Hello Ilona,

    I have tried with a 940nF capacitor but the only change is on the -10V voltage ripples. When the VGL voltage target is reached, with a 330nF output capacitor, we can see ripples on the output. Changing the output capacitor to 940nF only reduce the ripples.

    I will try with 1uF and 2uF output capacitors, I will come back to you when the test will be done.

    Best regards,

    Sébastien

  • 0 in reply to Sebastien.M
    Prodigy 130 points

    Hello Ilona,

    I come back to you about the VGL voltage power up. At start up, we get an undershoot on the VGL signal and it reach the -10V target. It append when the DVRN pin is driving.

    I try with the 1Uf and 2uF output capacitors and nothing change.

    Here a screenshot of the two signals:

    We did the test with the LCD screen plugged and unplugged. There are no differences on the signals.

    Is there a way tu cut this undershoot?

    Thank you

    Best regards,

    Sebastien