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TLV704: Load transient response and line transient response in dropout operation

Part Number: TLV704

Dears,

could you help to provide the curve of Load transient response(Vin 5V, Vout 5V) and line transient response(Vin 4V~6V, Vout 5V, Iout 50mA) in dropout operation, such as Vin 5V to Vout 5V.

thanks.

  • Hi Gary,

    While in dropout, the pass device is in the linear region of operation and the input-to output resistance is the Rdson of the PMOS pass FET. As such the output voltage will increase and decrease with Iout as the LDO is functioning similar to a resistor while in dropout.

    Vout will also follow any decrease in Vin directly. Again this is because Vout is equal to Vin - Vdo.

    When Vin exceeds 5.4 V (Vout + Vdo typ at 50 mA) the output will temporarily overshoot 5 V. When Vin is below 5.4 V, the error amp is driving the gate of the PMOS pass FET to its negative rail (GND) so that the FET is fully on. When the output reaches the regulation point (5 V in your application), the error amp must transition off the negative rail which takes time. During this transition the output will continue to rise causing an overshoot. The magnitude of the overshoot will depend on the slew rate of the line transient and amount of output capacitance.

    A slower slew rate allows the more time for the LDO to react to Vout being higher than the regulation voltage. Additional output capacitance will decrease the magnitude of the overshoot but increase the duration as the capacitors charge and discharge.

    Very Respectfully,
    Ryan