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TPS62160: 3.3V output voltage startup behavior is not matching expected behaviour

Abhishek singh
Expert 2000 points
Part Number: TPS62160


Hi,

Please find the attached schematic, we are generating various rail (5V, 1.35V, 3.3V and 1.8V), we are doing power sequencing using  PG output, When I am probing 3.3V rail,  I am not getting the result as per web bench simulation. (Snaps  are  attached, it is  taking almost 500ms to  ramp  up 3.3V )     

Schematic is not the exact replica of webench.  Kindly explain how extra components and their values will impact performance.

In one of the  board  we  observed one behavior which we could not  our 3.3 output  voltage first becomes stable at 1.8 V  for say  500 0r 600  ms then only it ramps  up  to  3.3V, (refer to  fig 2)if i  remove the load from this board by  removing power to processor and image sensor it shows behaviour similar to  fig 1

I have following question  

1) Does  value  of pull up resistance on PG pin could cause T

2) How does adding extra Cap on EN  pin and in shunt with feedback resistor impact performance.

Note: image 2  is showing 2.8 V as in image we probe after LDO  which is generated from 3.3V,  behaviour is same for input also.  

NIC_CARD _ P03_POWER_SUPPLY.pdf

  • 0
    TI__Intellectual 2415 points
    Hi Abhishek,

    unfortunately I cannot see schematic.
    Would you please share with us:
    - specification for each DCDC converter in terms of input, output voltage and load current
    - oscilloscope screenshot with input voltage, output voltage, PG signal and EN signal for critical DCDC converter
    -schematic and layout
    - is there any load connected to the output of DCDC converter during start up?

    Best regards

    Lubomir
  • 0 in reply to Lubomir
    Expert 2000 points
    Hi ,
    Lumbomir,
    Schemaatic .pdf is there between two images , Please let me know if you can download that .
    Specification for regulator is
    Vin 12 V
    Vout 3.3 V
    Imax 500mA

    Regarding load connectod
    I observed with load and without load ,
    1) in one board in both condition it is same as fig 1 ie Vout is ramping upto 3.3V with being stable at 1.8 V.
    2) in other board its behaviour is aas per fig 2 with load and aas per fig 1 without load .
    even with this wave shape device is serving our purpose , but after 5-6 months it starts giving problem ie image is not getting properly recorded , on restart it fixes , but once this problem arises it comes very frequently .

    As off now the two samples i am having don't have any problem as per functionality is concerned .
  • 0 in reply to Abhishek singh
    TI__Intellectual 2415 points

    Hi Abhishek,

    ramping of the 3.3V rail on the figure 1 (3.3V rail ramps to 1.8 and then to 3.3V) seems not proper operation.

    How is generated input voltage 12V?

    What is the maximum power which is possible to provide from this rail?

    As I said please share with me oscilloscope screen shot with following waveforms:

    • input voltage 12V rail (measured on C22)
    • input current for the rail VCC_12V
    • inductor current of L4
    • EN spin voltage on U7

    What is the output current for following voltage rails:

    • VCC_5V
    • VCC_1V8
    • VCC_1V35

    Best regards

    Lubomir

  • 0 in reply to Lubomir
    Expert 2000 points

    Hi  Lumbomir ,

    Please find the attached schematic. Previously i  thought that it is particular board specific issue,  because that time i have one board  only and this was part of  a  product which is in field since  last 4  year .

    But now i got 4 boards/products one  is not functionally working other are working, when i probed  3  working boards are giving correct waveform without load/ very low load ie without Vinci processor and image sensor but they are also showing similar behavior with the load.

    When i further debugged i realized we are making RC delay circuit for power sequencing of image sensor as well as the  processor. Due to delay circuit 3V3 rail   sshould be off  for 500 ms but during thaat time 1v8 is on  and both rail 1v8 and 3v3 are  going on processor  with other rail  . So i  am suspecting that 1v8 is leaaking / comming from processor on 3v3 rail   while  3v3 rail is off ie is why it is showing 1.8 rail  after  certain ramp up  when 1v8 gets  on .

    Below  is the image with charged  RC delay circuitry with other  rails 

  • 0 in reply to Abhishek singh
    Expert 2000 points

    Hi 

    Missed  to attach schematic  sch_501-1-00075_b2.pdf

  • 0 in reply to Abhishek singh
    TI__Guru**** 151860 points
    Thanks for posting this waveform. Are these the output voltages or EN pins?

    It looks like 1.35V comes up fine, but 1.8V takes its time. Can you zoom in on this and show 12V, 1.8V_EN, 1.8V_PG, and 1.8V on the waveform?

    Also, I noticed that you have a quite big resistor for the 1.8V PG. The EN input has a ~400k pull down which is connected when EN is low. With such a large pull-up resistor, you may not reliably have enough voltage on EN to register a high logic level.