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TINA/Spice/TPS53647: Cout voltage ramps up, while ICout is negative.

Andrey Bogdanov32
Prodigy 40 points
Part Number: TPS53647
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

Hi!

I'm simulating load transient response of TPS53647 based converter in TINA TI.

Model was exported from WEBENCH and slightly modified (added some meters, added current generator).

Below are screenshots and TINA schematic.

The question is how is it possible that VF2 (VCout) begins ramping up(cursor A), while current through capacitors is still negative (it crosses zero at cursor B)? What am I missing?

2018_07_16.tsc

  • 0
    TI__Expert 4060 points
    Hi Andrey,

    By looking only at the capacitor current you're missing the larger picture during the load step. While the capacitor current is dropping to try to keep the output voltage held up, the controller and inductor are also playing a role.

    The inductor is still charged with energy when the load step hits and this gets passed into the load as it's also connected to VF2. This mostly limits the output voltage from dropping further but keep track of the currents is important.

    Once the controller finally responds to the load step, the red cursor, it does so by keeping the upper FET turned on more and letting the inductor current increase further. This is where your extra current comes from.

    I_inductor flows into the node, I_caps flows out of the node, I_load flows out too but I_inductor is larger than both currents so VF2 rises as the caps charge.

    Let me know if you have any questions.

    Cheers,

    Carmen
  • 0 in reply to Carmen Parisi
    Prodigy 40 points

    Hi, Carmen!

    I will try to state my question one more time:

    1.ICout is negative left to red cursor, which means current flows from capacitor bank, which means this current discharges caps and voltage over them falls. This is ok.

    2. ICout is negative between red and blue cursors, which means current flows from capacitor bank, which means this current discharges caps. But cap voltage rises, which means caps charge. How can be capacitor charged with discharging current?

  • 0 in reply to Andrey Bogdanov32
    TI__Expert 4060 points
    Hi Andrey,

    I might not have made my original explanation as clear as I could, sorry about that. Recharging the caps will come after the load currents and VOUT have stabilized later in time. To understand what's happen you have to step back and look at first principles like Ohm's Law and Kirchoff's Law.

    VF2 and VF1 are actually the same node, VOUT, just with the current probe in place between the caps and the output voltage. Since it's an ideal probe it doesn't drop any voltage across it and looks like a 0Ω resistor. There are then several current paths to take into account, you can't just look at the caps in a vacuum.

    So, at this node there are the following currents flowing in an out of it:
    1) I_inductor -> flowing into the node and increasing as the control responds to the transient
    2) I_capacitors -> flowing into the node as the caps discharge
    3) I_transient -> transient load current flowing out of the node, fixed since it's an ideal current source
    4) I_DC -> Load current drawn by the resistor flowing out of the node

    I_inductor + I_capacitor are going to be more than the transient current summed together since they were already providing the static load current plus AC ripple so the excess has to go somewhere which means those currents flow through the resistor. From Ohm's law more current through a resistor means higher voltage and VOUT will rise.

    There are also second order effects at play too. The load step will excite the resonant RLC circuit (inductor + DCR, 100uF caps + ESR, 470uF caps + ESR, static load R) and as that rings out before the controller takes over VOUT will swing up and down.

    Cheers,

    Carmen