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TPS65910: Accessing RTC registers

Part Number: TPS65910

I am attempting to use the RTC registers in the TPS65910 and having some difficulty.  I am properly addressing the device as it ACKs the command and register select bytes.  It returns 0x00 for all register reads, even where the default is non-zero.  I assume I am doing something wrong.  I scoured the data sheet for clues, but found documentation on the I2C operation somewhat sparse.  I have some questions:

  1. How is the register address sent to the PMIC?  I am assuming it is sent as the first byte after the address/write command byte.  Is this correct?
  2. Does the register address auto-increment after a byte is written or read?  (I tried reading multiple bytes, and also multiple single byte write register address/read a byte operations)
  3. Is dropping the STOP signal in between the write register address and read command allowed, or must I write the register address with a STOP signal before issuing the read command?

It would be nice if the above information were included in the data sheet and/or an explicit signalling diagram were included.

Gerry Belanger

  • Hi Gerard,

    The TPS65910 should be fully compliant with I2C specification (www.nxp.com/.../UM10204.pdf), so that document will likely prove more useful than the notes placed in the datasheet but it's a bit dry. There is a generic app note www.ti.com/.../slva704.pdf that is a bit more useful.

    1. Figure 9 in the SLVA704 document shows a good diagram of this. Basically it's 7bit Device address (0x2D = 0b0101101) + r/w=0 + ack, 8 bit register addres + ACK, repeated start, 7 bit device address + r/w=1 + ack, then data should come out of the TPS65910.

    2. I'm not sure if TPS65910 supports repeated read / repeated write.

    3. You should not need a STOP, but you will need a Repeated Start.

    Most of our more recent datasheets contained more on the I2C, I've added a note to try to add that to this datasheet if another revision is made in the future.

  • Kevin,
    I have more information. I expanded my read loop to cover all of the PMIC registers up to the JTAGVERNUM_REG at offset 0x80.
    It looks like I am reading valid data for the PMIC registers from the PUADEN_REG at offset 0x1c up to the JTAGVERNUM_REG.

    This means I am driving the AM335x I2C controller correctly. I get the same result whether I send a STOP after writing the register address or go directly to the repeated START. So I2C communications is not the issue.

    I am still not seeing any of the non-zero reset default values for any of the RTC registers. According to the PMIC data sheet, there are 6 RTC registers which should have non-zero post reset default values. All are reading zero. This is the actual problem. Suggestions welcome.
  • Hi Gerard,

    Are you reading values from any registers other than VDD1_OP_REG (0x22) or VDD2_OP_REG (0x25)? If those are the only two, it might indicate that you are using the SmartReflex I2C bus instead of the normal I2C bus.

    I just took screenshots of an I2C read from the "DAYS" register (0x03) which has a default of 0x01, can you compare them to your scope shots and see if anything is missing?

    Zoomout:

    Zoomin1:

    Zoomin2:

    Zoomin3:

    Zoomin4:

  • Kevin,

    I am pretty sure I am addressing the correct device.  When I read register 0x1c, PUADEN_REG, the code sees 0x9F, the default value.

    On register 0x03, I see a similar scope trace to yours.  The '1' bit is there, but the 0x01 expected is not showing up in the I2C controller read data register.  So this no longer looks like a PMIC problem. 

    I will have to investigate what is different from the AM335x I2C controller POV when reading the RTC registers vs the remaining registers. 

    Probably an oversight on my part, but I will delve into it later this week.

    Thanks for your help

    Gerry Belanger

  • Hi Gerry,

    Good to hear that the PMIC is sending the correct information, thank you for the update. Good luck with the software side!

  • Kevin,

    The problem turned out to be the DEVCTRL register.  Specifically the RTC_PWDN and CK32K_CTRL bits.  These both default to '1' in the TPS65910A3A1 configured with BOOT0 = 0, and BOOT1 = 1.

    The RTC_PWDN bit removes power from the RTC subsystem.  The CK32K_CTRL bit selects the RC oscillator instead of the 32.768 crystal.

    Setting both of these bits to '0' allowed the RTC to work properly.

    It would have been helpful if the functional description of the RTC in the data sheet mentioned this tidbit.

    Gerry Belanger