This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS650250: About current waveform

Part Number: TPS650250

TPS650250 current waveform of DCDC1.pdfHi to whom it may concern,

 

I ask about current waveform of TPS650250.

Could you please confirm attached file about detail.

 

(Question)

1, When the voltage rise up, the current reached about maximum output current value.

     After that the current value is fall down.

     Is this correct?

 2,  If it is not correct, could you please teach the cause and how to resolve?

 

I think that soft start is not working.

Is this because the time from voltage input to Vbat to access to Enable pin is long?

 

Could you please give me some advices?

 

Best regards,

Gk110

 

  • What is the load on DCDC1 converter? What is it powering in your test?

    What is part # of your input and output capacitors? Datasheet says 10uF and 22uF, but the voltage rating is also important.

    Soft-start time is 750uS from 5% to 95% output voltage, shown on page 8 of TPS650250 datasheet (tSS, Soft start ramp time). From you scope shot, it appears that the ramp time is correct, but the load is very heavy during this time. The load measured (1.58A) never exceeds that max current of DCDC1 (1.6A), and again this looks acceptable.

    To me, there is no issue, and I cannot assist further without knowing more about the system (load, enable timing of load, capacitor part #).
  • Hi Berner-san

     

    Thank you for your reply prompt.

     

    > What is the load on DCDC1 converter?

     

    --> The load is Vcco of FPGA and logic IC.

     

    I understood that is no problem because the current never exceeds that max current of DCDC1 (1.6A).

     

    However I’d like to ask about soft-start at TPS650250.

    I have thought that the soft-start is effect for prevent steep rise-up of current.

    But this time was not prevent.

     

    Is my understanding wrong?

     

    Could you please answer?

     

    Best regards,

     

    Gk110

  • The purpose of soft-start is to prevent too much current that would cause the output voltage to droop and/or overshoot in response to the load.

    In addition, soft-start will prevent the FETs from experiencing the Forward Current Limit (ILIMF), which would cause the DC-DC converter to shut down and re-start. If the converter hits the ILIMF value on turn-on, it is possible it would get stuck in an infinite loop.

    This e2e Blog Post explains soft-start at a high-level: 

    The term "steep rise of current" is relative. But the terms "steady monotonic rise in output voltage" and "ILIMF" spec are absolute. You always want to see a "steady monotonic rise in output voltage" and you do not want to see the current exceed ILIMF, which for the TPS650250 is 1.75A (minimum). Since both of these conditions are met and the DC-DC converter does not shut down unexpectedly, the soft-start feature is working correctly.

    I would need to see your schematic and BOM to understand what is happening in your system specifically.

  • Hi Berner-san

    I got additional information from our customer.

    Could you please refer to the attached file for the detail of the circuit?

    They would like to know why this phenomenon occurred.

    Could you please explain the cause?

    Best regards,

    Gk110

    TPS650250 current waveform of DCDC1 rev2.pdf

  • Gk110,

    In your PDF, it says "R1,R2 --- Not connect"

    How is the DEFDCDC1 pin terminated? It should be tied directly to VCC (which should be same as VBAT or main VIN).

    This is why we ask for the customer's schematic. It is not identical to the example schematic shown in the datasheet. All of these differences could be important, and I cannot see differences when the customer's schematic is not shared.

    Also, Part # GRM188B31A106ME69D does not show up on any distributors websites (Mouser, Digikey, etc). If I cannot find the capacitor, I cannot verify its specifications.
  • Berner-san

    First, I'm sorry I mistake about R1,R2.

    It is correct as follows.

    R1,R2 is unimplemented.
    I requested to share the schematics of customer.
    When I recieved it, I will try to share it soon.

    Also, GRM188B31A106ME69D is MURATA's capacitor.
    Could you please check the following site.

    Best regards,

    Gk110

  • Gk110-san,

    I have tested this in the lab on an EVM, and I can re-produce results that are very similar to the customer's scope shot. 

    The load of 1.05A is applied immediately as the voltage begins to ramp. The voltage rises consistently from 0 to 100% of the desired output within the expected "soft start time of 750us, and the voltage never collapses because the max current is never exceeded.

    My conclusion is that this behavior is expected and will not cause any issues

    Ch1 = VIN, Ch2 = VDCDC1, Ch4 = IDCDC1 (Load current)

    If the customer does not want to see this pulse of current, they need to manually delay the IC which is applying the load on the DC-DC converter. Most ICs have an Enable pin that will prevent them from applying the full load until the output voltage has increased above a certain threshold. Each DC-DC converter has a Power Good bit in the Register Map which can be read by I2C. When DCDC1's Power Good bit = 1, then the full load can be turned on.