Hi,
I am getting confused about PWRHOLD's connection. As the datasheet description it should be connected to VIO to maintain power rails output (that is what I am doing), however the link below about a reference design pulls up this pin to VTRC instead:
http://designsomething.org/craneboard/w/hardware/default.aspx
Since VRTC is an always-ON rail it will never get chance to have PWRHOLD back to zero, how the power-off process could be implemented (software controlled)?
The datasheet also confused about its power domain: on page 3, it is described as "PWRHOLD IO is supplied from VDDIO". On the page 37 however table 11 gives that PWRHOLD supplies is from VRTC/DGND. So which one is right?
I have problem to see PWRHOLD back to zero (connected to VDDIO) after DEV_OFF bit is set. VDDIO only falls down to about 0.8V about 3.5mS, and this residential voltage triggered another power on process so PMIC is powered on again. What is the possible root cause?
Someone help please!
Thanks
Jiansheng