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LM5070: Startup failure

Part Number: LM5070

Having transferred the 'Synchronous Rectification' circuit from the datasheet to a PCB, I find that it doesn't seem to work. Plugging in a POE cable causes a voltage between UVLO and UVLORTN of 2.7V, which I think means that it was correctly recognised as a PD. My understanding is that the next step involves RTN being 1.5V below VEE, which doesn't seem to happen. There's mention of a charging load capacitor that has something to do with this but no description of where this capacitor is so I might have missed something.

I notice that VCC to local ground is 7.8V, COMP is seeing a sawtooth waveform of around 1.25V mean and that OUT is emitting a series of pulses at ~250kHz. I mention this because I might have completely misunderstood the order in which the IC starts up and the actual issue might be something else. I should clarify that there appears to be no significant voltages on the other side of the transformers and total output is zero volts.

Obviously there's a mistake or a fault somewhere, could anyone help me by pointing out where it's likely to be?

Thanks for your time.

  • Hi Meilyr,

    If the PSE turned ON then the PD passed detection and started up which means the PD controller side is okay.

    If the voltage between pin 7 and 16 is NOT ~0V, then their maybe some overcurrent/short on the DCDC converter side. This can also be seen if the converter is unable to start switching or VCC cannot stay above its UVLO threshold.

    You may need to check that connections on layout is the same as the schematic and that there are no shorts or possible incorrectly populated components/value.
  • Hi Daniel,

    Thanks for helping. I appreciate it.

    First, apologies for not making this clear: by 'RTN' I meant pin 8, which is so marked on the datasheet I have. The 1.5V I mentioned is, to my understanding, a voltage introduced by the chip as part of the startup procedure. Taking a closer look with an oscilloscope I can see a transient which includes a brief stop a 1.5V between pins 7 and 8, so it is passing that step after all. Seems to have a lot of ringing and other bouncing around, though: not sure if that's part of the design. Once things have settled down the voltage between the pins is zero. Looking at OUT the pulses I mentioned are actually a series of step waves approximately 15us in width with quite a lot of ripple.

    I've double-checked the connections on the layout and examined the circuit with a continuity tester and visually under a microscope. I can find no faults with either the layout or the construction.

    EDIT: I've made a further discovery: pin 13 (CS) is periodically experiencing a pulse with a peak just over 0.5V, which means that the chip stops the output pulse. The timing is consistent with what I've seen on OUT. The components are the correct values, the schematic is correct and further visual inspection revealed nothing. When the datasheet says that the current filter, especially the capacitor, must be very close to the chip: how close is very close? Would a ~10mm distance be catastrophic?

  • Hi Meilyr,

    It sounds like the converter is trying to startup but shuts down either from a fault on the primary side or secondary because VCC can't stay above 8.1V after switching starts.

    I don't expect 10mm distance of the RC filter of the CS pin to be catastrophic. But you can remove the cap and blue wire it closer to the IC to see if it improves the failure.
  • Hi Darwin (not Daniel! Sorry about that),

    I've since discovered that the primary issues with my circuit was incorrect choice of transformers (should have been T1:C1023-A and for T2 SM76925 has gone obsolete so I replaced it with B82804A0264A210) and wrong pin ordering on the optocoupler.

    However, while I do get a steady PWM train most of the time the chip seems to randomly change the output waveform to one of two others.

    Below is the usual. Blue is output (3.3V pin) while red is the secondary dot pins of T1. I've confirmed that is the waveform coming out of the chip's OUT pin.

    It then randomly changes to the below, so far as I can see with no external stimulus. It generally settles here for a minute or so.

    Then changes again to the below, which is similar but noticeably different. After doing this for ten or twenty seconds it goes back to the first waveform for a while.

    All three conditions are stable (that is, the chip is consistently outputting the same waveform for the duration) until it changes from one condition to another. Where probes are connected seems to alter the behaviour, such as not connecting a probe to the output appears to make it far less stable.

    This looks like the chip is hovering right at the edge of some transition between states. Does anyone have any suggestions as to what's going on?

  • This looks like some instability. Can you send your schematic? Thanks!
  • The schematic is attached. The actual circuit has a number of wires and such going from one place to another, but I'm as sure as I can reasonably be that this is a faithful depiction.

    Thanks again for your help.

    4705.Power.pdf

  • Hi Meilyr,

    Nothing caught my eye regarding the schematic as it is a copy of the past LM5070 EVM. It may be something more on the board is not the same (or damaged) as the schematic.
  • Meilyr, It has been over a week since there has been activity on this tread. As our Application Engineer suggested, without further information, we suspect damage and/or schematic differences (to the actual board in question).

    Do you have any additional information which might prove helpful to us?

    If not, I think we are at a loss to help trouble shoot further and I would propose we close this thread.
  • I have nothing in particular to add. Given that I have had to make a number of manual alterations to the board damage is certainly possible. We'll see how it comes out when manufactured. I'd be happy to close this thread.

    Thanks for all your help.
  • You are welcome. Please contact us again once you have manufactured boards in hand and see any concerning behavior.

    Best of Luck,