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TPS3511: Delay undervoltage protection

tom
Prodigy 200 points
Part Number: TPS3511

Hi,

I have a question on the TPS3511 regarding PGin and the undervoltage lockout feature.

When the TPS3511 is enabled by %PS_ON the delay for undervoltage protection is 75ms.

This is enough time for all the powersupplies (12V, 5V and 3.3V) to start-up.

The supervisor also has a PGin to disable PGout and undervoltage protection fast in the event of input power failure.

However when the PGin goes high again the undervoltage protection delay is only 3.2ms (minimal)

This seems short to ramp up all the powersupplies of a ATX powersupply, am i misintepreting the use of PGin or is this short power-up time intended?

best regards,

Tom

  • 0
    TI__Genius 12630 points

    Tom,

    According to the datasheet on page 8, when PGI (input) goes high, the delay before PGO (output) goes high is 150ms typical. The delay you refer to is from PGI going high and FPI (failure protect output) which is intended to be quicker than the power good output (PGO) delay.

    Does this answer your question? Please let me know if you have any more questions. Thanks!

    -Michael

  • 0 in reply to Michael_DeSando
    Prodigy 200 points

    Hi Micheal,

    Yes the delays you mentions are correct.
    The problem i have is with PGI input going high to undervoltage protection enable being only 3.2ms.

    This means the 5V and 3.3V voltage rails need to be started in that time-frame, which is too fast for my case.

    I want to use the PGI input to signal loss of input power, however when the input power restores UV protection is enabled after 3.2ms.
    The UV protection timer is alot longer when %PS_on is toggled or ic is reset by POR. (75ms)

    In figure 1 (page5) power supply ramp up (Tt) maximum of 20ms is specified.

    Am i using the PGI input incorrectly? How is it normally used?


    best regards,
    Tom

  • 0 in reply to tom
    TI__Genius 12630 points
    Tom,

    You mention "The problem i have is with PGI input going high to undervoltage protection enable being only 3.2ms.

    This means the 5V and 3.3V voltage rails need to be started in that time-frame, which is too fast for my case."

    This is not true. If 5V or 3.3V rails are low, /FPO will still be active. The failure power output (/FPO) pin only releases when PGI comes up AND the 5V, 3.3V, and 12V rails are also up.

    You can also use PGO output to signal "power good" for PGI pin but /FPO will signal a failure if 3.3V, 5V, 12V or PGI rails are bad.

    -Michael
  • 0 in reply to Michael_DeSando
    Prodigy 200 points

    Hi Micheal,

    "This is not true. If 5V or 3.3V rails are low, /FPO will still be active. The failure power output (/FPO) pin only releases when PGI comes up AND the 5V, 3.3V, and 12V rails are also up."
    From diagram on page 3 the /FPO is latched fault state, it only resets/releases on POR and %PS_ON toggle right?
    PGO comes up when 5V, 3.3V are up and PGI is up (after 150ms delay)

    Maybe i can explain it more clearly in a scenario:
    Powersupply with 12V, 5V, 3.3V voltage rails, %PS_ON and PGO connected to motherboard.
    PGIN has voltage divider on input voltage so it detects 16V input as logic high.
    Inverted /FPO is connected to DC/DC converter enable pins and converter has 15V UVLO set.

    1. Input power (24V) is applied. PGIN high, %PS_ON is high and PGO low and /FPO high.
    2. %PS_ON pulled low. After 38ms /FPO resets and is pulled low. DC/DC converters start and after 75ms UV protection is enabled and after 150ms PGO is high. (Powersupply has started correctly)

    3. Input power is removed, and input voltage drops below 16V. PGIN is low and PGO goes low after 150u, /FPO is still low.
    4. Input voltage drops below 15V and voltage rails are discharged. PGO and /FPO still low.
    5. Input power is reapplied before it drops below 5V. Now there is only the 2.3ms timer before UV protection is enabled. Voltage rails have not started 5V and 3.3V yet and /FPO is latched high due to UV. (Powersupply has not restarted correctly and stays in fault state)

    I hope i explained it clear enough.
    I think i am missing something or i am not using PGI pin as was intended?

    best regards,
    Tom