Hi,

Which SDK (and its version) are you using for CAL?

Regards,

Brijesh

ti-processor-sdk-linux-automotive-dra7xx-evm-6.00.00.03 , I another post  https://e2e.ti.com/support/processors-group/processors/f/processors-forum/999037/dra722-dra722-csi-virtual-channel described

Hi,

Yes, there are examples in vision sdk, which uses cal virtual channel feature. Please refer to the iss specific usecases in vision sdk. Wherever multiple cameras are used in iss usecase, it uses cal virtual channel feature.

We dont really need to worry about cport id in application, this is internally taken care inside the driver.

Again, we dont need to process DMA interrupts, this is taken care by the driver. 

Regards,

Brijesh

1. Because in ti-processor-sdk-linux-automotive-dra7xx-evm-6.00.00.03 , Linux driver of cal dont support virtual channel, so I try to modify the driver , need to manage the cport and DMA .

2. I am try vision sdk ,but many problem when using CCS debug , https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1001698/dra722-vision-sdk-debug-on-ccs/3700498?tisearch=e2e-sitesearch&keymatch=%2520user%253A109537#3700498

Hi,

Could you please check the PDK driver and CAL example in the PDK driver? Example also supports multiple channels using virtual channel id. 

In fact, vision sdk internally uses PDK driver to configure CAL module.

You could find this example in ti_components\drivers\pdk_xx_xx_xx_xx\packages\ti\drv\vps\examples\iss\captureIss folder. You could even run this example from CCS.

Regards,

Brijesh 

Is there any document about how to configure CAL 's cport and DMA  in detail

This example is run M4 or A15? how to build and running? my board is custom board.

Hi.

This example runs on M4, you could even load and run it on custom board, if you have gel files for this board.

Please refer PDK user guide, which explains how to run examples using CCS. It is available at https://processors.wiki.ti.com/index.php/PDK/PDK_TDA_VPS_User_Guide

Regards,

Brijesh

I am sorry , the link is fail :

This Page Does Not Exist

You could even check it in 

vision_sdk/ti_components/drivers/pdk_xx_xx_xx_xx/docs/userguide/html/PDK_TDA_VPS_User_Guide.html

Rgds,

Brijesh

Thanks

I am reading the pdk code and try to porting to my custom board , TI's code is not very clear, so porting need long time,but my project deadtime expired. 

ths pdk 's vps , looks like cport is 1,2,3,4 , using ctx0 to ctx3 , and DMA start/end 0 to 3 , it's the same thing I did, I dont know why only dma interrupt generated, is it the MFLAG setting error? I keep it default value 0xff .

Is there any application note or other document about CAL? thanks

Hi,

Does the single channel input work fine in your case? Then can you try two channels? If possible, can you share CAL register settings? 

You could refer to CAL specs in the TRM.

Regards,

Brijesh

using ti-processor-sdk-linux-automotive-dra7xx-evm-6.00.00.03 ,single channel input can work fine, I modify the cal driver , CAL register settings :

Registers @ 0x0x000000004845b000:
00000000: 40000200 a3c90469 00000000 00000000
00000010: 00000004 00000000 00000000 00000000
00000020: 00000000 00000000 00030000 00030000
00000030: 00000000 00000000 00000001 00000001
00000040: 0000000e 00000000 00000001 00000001
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00000000 00000000
00000070: 00000000 00000000 00000000 00000000
00000080: 00000000 00000000 00000000 00000000
00000090: 00000000 00000000 00000000 00000000
000000a0: 00000000 00000000 00000000 00000000
000000b0: 00000000 00000000 00000000 00000000
000000c0: 00050014 00150015 001d0015 00250015
000000d0: 00000000 00000000 00000000 00000000
000000e0: 00000000 00000000 00000000 00000000
000000f0: 00000000 00000000 00000000 00000000
00000100: ff1fe07e 00000000 00000000 00000000
00000110: 00000000 00000000 00000000 00000000
00000120: 00000000 00010000 00000000 00000000
00000130: 08080000 00000000 00000000 00000000
00000140: 00000000 00000000 00000000 00000000
00000150: 00000000 00000000 00000000 00000000
00000160: 00000000 00000000 00000000 00000000
00000170: 00000000 00000000 00000000 00000000
00000180: 00000000 00000000 00000000 00000000
00000190: 00000000 00000000 00000000 00000000
000001a0: 00000000 00000000 00000000 00000000
000001b0: 00000000 00000000 00000000 00000000
000001c0: 00000000 00000000 00000000 00000000
000001d0: 00000000 00000000 00000000 00000000
000001e0: 00000000 00000000 00000000 00000000
000001f0: 00000000 00000000 00000000 00000000
00000200: 00004000 fd600000 00000000 00000000
00000210: 0b404504 fd600000 00000a00 0a000000
00000220: 0b404704 fd600000 00000a00 0a000000
00000230: 0b404904 fd600000 00000a00 0a000000
00000240: 00004000 00000000 00000000 00000000
00000250: 00004000 00000000 00000000 00000000
00000260: 00004000 00000000 00000000 00000000
00000270: 00004000 00000000 00000000 00000000
00000280: 00000000 00000000 00000000 00000000
00000290: 00000000 00000000 00000000 00000000
000002a0: 00000000 00000000 00000000 00000000
000002b0: 00000000 00000000 00000000 00000000
000002c0: 00000000 00000000 00000000 00000000
000002d0: 00000000 00000000 00000000 00000000
000002e0: 00000000 00000000 00000000 00000000
000002f0: 00000000 00000000 00000000 00000000
00000300: 00000001 6a053214 00000000 00000000
00000310: 5fffffff 00004197 3f3f3f3f 00000000
00000320: 00000000 00000000 00000000 00000000
00000330: 00000000 00000241 00000381 000004c1
00000340: 00000000 00000000 00000000 00000000
00000350: 00000000 0000000b 0000000b 0000000b
00000360: 00000000 00000000 00000000 00000000
00000370: 00000000 00000000 00000000 00000000
00000380: 00000000 00000000 00000000 00000000
00000390: 00000000 00007fff 00000000 00000000
000003a0: 00000000 00000000 00000000 00000000
000003b0: 00000000 00000000 00000000 00000000
000003c0: 00000000 00000000 00000000 00000000
000003d0: 00000000 00000000 00000000 00000000
000003e0: 00000000 00000000 00000000 00000000
000003f0: 00000000 00000000 00000000 00000000

cal: CSI2 Core 0 Registers @ 0x000000004845b800:
00000000: 01000626 e202e10e 000000ff 7df7c0a0
00000010: 739ce738 806ae204 02093000 00040200
00000020: 65180000 00000000 00000000 00000000
00000030: 00000000 00000000 00000000 00000000

Hi,

Looking at the register, i see CAL is configured for 3 channels and all 3 channels are capture some frames. Because you could see frame is toggling at below location.

00000350: 00000000 0000000b 0000000b 0000000b.

Even the Write DMA is configured for 3 channels., but all of them are writing to the same buffer address, this could be reason why you are not getting callback. can you set different buffer address for each of them?

00000200: 00004000 fd600000 00000000 00000000
00000210: 0b404504 fd600000 00000a00 0a000000
00000220: 0b404704 fd600000 00000a00 0a000000
00000230: 0b404904 fd600000 00000a00 0a000000

Regards,

Brijesh

OK, I will update the driver to set different buffer address,but I configured for 4 channels, channel 0 's DMA work right, In isr callback I read register CAL_HL_IRQSTATUS_1 and CAL_HL_IRQSTATUS_2 , only DMA start/end 0 bit is set, others are zero.  When DMA start interrupt generated, I will update the DMA address. 

But it seems camera0 is not configured and does not seem to be capturing.

DT and VC are not configured for Camera0

00000330: 00000000 00000241 00000381 000004c1

No frame counter/status for camera0

00000350: 00000000 0000000b 0000000b 0000000b

Rgds,

Brijesh

Sorry, This is my test , I want to determine if the DMA start/end 0 interrupt too frequently blocking other channel interrupt, so I closed the ctx0,but there is no DMA start/end interrupt generated now.

ok, can you try after fixing buffer address issue?

Regards,

Brijesh

I fixed the dma buffer address issue and turn on all channel DMA start/end IRQ , I can capture all virtual channel video , Thank you very much!!!

By the way, there are 8 context but only 4 pix_proc , how to configure the pix_proc when more than 4 channels, can be bypassed?

Great, glad to know it is working fine. 

You could disable pixel processing context and store the input as it is using DMA channel, but only if input format is in YUV422 or RAW8 format. 

RAW10 and RAW12 formats requires to use pixel processing context. 

Regards,

Brijesh

It will be disabled the pixel processing context if I ignore the pix_proc setting directly?

No, set the enable flag in pix_proc setting to explicitly false, then it will be disabled.

Regards,

Brijesh

It means that I need to configure pix_proc 's cport associated context , then set the CAL_PIX_PROC_i's EN bit to disabled status ? 

Yes, set the EN bit in PIX_PROC register to disable it.

Rgds,

Brijesh

I want to know if I need to occupy a PIX_PROC resource then set EN bit to disable it, or ignore the PIX_PROC setting when not need pixel processing. 

Thank you for your patient help!