Our customer was developing their system with TMS320C5517. For their system, they are using External clock input dn the desired SYSCLOCK is generated by PLL/CLOCK Generator. If there are some omission/toothless clock in this input-clock, would you expect what kind of adverse-effects occurs ?
The following is that customer's expectation.
- C5517 is working as normal operation unless PLL has "Phase Lock Lost"
- If PLL has "Phase Lock Lost", customer considering that C5517 transits to BYPASS Mode.
- C5517's core is working as normal operation with CLKIN's frequency.
- Also, DMA controllers and other functions are working as normal operation
- For peripheral, however, It is affected by the decrease of SYSCLK from the frequency at PLL_MODE to the frequency of CLKIN.
For example, in the case that McBSP is working with external clock/frame signals, there is possibility that the relationship of operation-timing between DSP's DMA(SYSCLK domain) and McBSP(External clock base) will be broken. As the result, DSP would be malfunctioned
Howe would you consider customer's expectation ?
Can I have your Expert's advice/comments on this, please?