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L1/L2 Caches using

Alexey Govorukhin
Prodigy 180 points

Other Parts Discussed in Thread: AM3517

Hello everyone!

I am trying to use  the L1/L2 Caches in our Bootloader to speed up the boot process of AM3517 micro.

Is there any examples of code, how exactly to use this caches? (Initialization, flushing, Invalidating, etc)

 

Thanks in Advance,

Alexey

  • 0
    Prodigy 50 points

    Hello!

    Where there is, I also want to!!!!

  • 0 in reply to Jun Feng Xu
    Prodigy 180 points

    Does really no one knows about it?

     

  • 0 in reply to Alexey Govorukhin
    TI__Mastermind 44306 points

    There is some code in u-boot.

    Otherwise you can refer to ARM TRM docs on their website.

    Regards.

  • 0 in reply to Frank Walzer
    Prodigy 180 points

    Thanks for the answer, Frank.

    As I understand, u-boot does not uses it.

    I didn't found the place, where the tables L1 and L2 for MMU created. And where MMU switched on.

    MMU uses the tables to know, which memory area to be cached, and which not.

     

    Is there a such place?

     

    Thanks in advance,

    Alexey

  • 0 in reply to Alexey Govorukhin
    TI__Mastermind 44306 points

    MMU setup is a different story. The MMU table setup has to be done to enable L2 data caching and define appropriate cache modes.

    U-boot does not use the MMU as far as I know as it is a single process only.

    Now in Linux there is for sure use of MMU but that is dynamic due to the use in protecting processes from each other. We do have some static MMU table setup code but it has some other dependencies (e.g. Sys/Bios 6 for ARM where MMUs and setup are supported).

    Again you might refer to the ARM TRMs which explain the Cache/MMU scheme in detail (there is no other doc on this from TI). Then it is a matter of setting up the TLB tables in memory and correctly enabling cache and MMU. Examples for this are usually tools dependent as it is done using assembly language.

    Regards.

  • 0 in reply to Frank Walzer
    TI__Expert 8180 points

    Hi,

    Another reference I can suggest here is, refer to the kernel uncompressing code "arch/arm/boot/compressed/head.S".

    Thanks,

    Vaibhav

  • 0 in reply to Vaibhav Hiremath
    Prodigy 180 points

    Thank you for the answer, Vaibhav!

    I did try the code from  "arch/arm/boot/compressed/head.S" file. But it did not turn on MMU, only D- and I-Caches.

    I did also tried  the code from examples from ARM Developer guide, where the flat model was used in tables. This examples are working, but only till the point of jumping in to loaded code: Bootloader works fine, and when it tries to jump into loaded code, it stucks, some times micro resets it self.

    Of course I did tried to turn off caches before the jump, I did try also the procedure of turning the caches off from the   "arch/arm/boot/compressed/head.S", but after that  whole RAM was corrupted.

    Is there an examples, or guidelines on how to turn caches off in right way?

     

    Thanks in advance,

    Alexey