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OMAP-L137: How to confirm if the value of external pull is ok

Part Number: OMAP-L137

Hi

It seems that the internal pull-down for pin# T3 is enabled by HW and it's not configurable by SW.

https://www.ti.com/lit/ds/symlink/omap-l137.pdf Table3-19:

User uses this signal as Input, and it is tied to 3.3V vie 10kΩ outside the device.

We don't know how much the internal resistance value for this pin is, and I'm afraid if this pin is floating with these internal pull-down and external 10kΩ pull-up.

Please advice how to confirm if it's ok or not.

Thanks and Best regards,

Tsurumoto.

  • Hi

    Please ignore my previous question above.

    User already knows that the signal is floating by these internal pull-down and external 10kΩ pull-up,

    Then, would like to know if it damages to SoC or not.

     And also, would like to know how widely damage inside SoC by this behavior. 

     

    Thanks and Best regards,

    Tsurumoto.

  • Tsurumoto-san,

    What is the voltage of the T3 pin when probed at the 10kO resistor? Check it on multiple boards.

    If the voltage is between VIL (0.8V) and VIH (2V) due to contention with IPD and external 10k pull-up, this condition may lead to reliability issues before the device reaches its Recommended Power-On Hours.

    Table 5.5 in the OMAP-L137 datasheet specifies "Input current" for conditions "with opposing internal pulldown resistor". This current plus a small input leakage (~35uA) would have to flow through the external pull-up which could result in a significant voltage drop for the 300uA "max" current. But for the 50uA "min" current, I expect the voltage will be above VIH (2V). If the voltage at the input buffer is between VIL and VIH, then both PMOS and NMOS regions of the input buffer are partially on with current flowing from VDD to GND, leading to reliability issues after some time. The IPD is implemented with transistor, which is more "On" when the voltage on the pin is at its highest. As the voltage comes down, the IPD becomes weaker. See E2E: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/81850/about-internal-pullup-pulldown-resistor-value-of-am3517

    For a different device (AM572x SR1.0), TI published an errata for MMC_DATn pin which had an IPD enabled after reset but requires an external pull-up for MMC operation. In that errata, we explained that leakage through the both partially on PMOS/NMOS parts of the input could consume upto 2mA per buffer at 3.3V. For that device, we recommended that this condition of contention can last a maximum of 200 hours in a device life cycle. I suspect the advice would be similar for this device. Refer to SPRZ429M i863 MMC2 Has PU/PD Contention Immediately after Release from Reset
    https://www.ti.com/lit/er/sprz429m/sprz429m.pdf

    We would need to reach out to the quality team to learn the maximum time this device can tolerate the mid-supply voltage at an input buffer. And to understand the extend of the potential damage. I will ask if damage should be limited to that IO cell or more broad.

    If this pin is not used, maybe it could be enabled as a GPIO output and drive a logic high with software (use the PFUNC Pin function register to define this pin as a GPIO). The drive strength of the output buffer will bring the voltage > VIH and eliminate the leakage path caused by PMOS/NMOS being both partially on at the input buffer. Even if this pin is used as an input, maybe it can be configured as an output for most of the time and only configured as an input when polling the state of the pin. This would delay the reliability concerns caused by mid-level input voltage.

    See also 4.3 Pullup/Pulldown Resistors in the datasheet. A 1K external pull resistor is recommended to counter an internal pull resistor, and 20K is recommended to compliment an internal pull resistor.

    Hope this helps,
    Mark

  • Hi Mark

    Thanks to sharing above information.

    >What is the voltage of the T3 pin when probed at the 10kO resistor? Check it on multiple boards.

    T3 pin is signed as GPIO input with internal pull-down and external 10k pull-up.

    And, if the voltage of the pin  is

        1.827V  ==> GPIO input signal is detected as High

        1.783V  ==> GPIO input signal is detected as High 

        1.741V  ==> GPIO input signal is detected as High

        1.725V  ==> GPIO input signal is detected as High

        1.488V  ==> GPIO input signal is detected as Low

        1.457V  ==> GPIO input signal is detected as Low

    From the above voltage results,  how was the transistor for internal pull-down working?

    I have another question related to threshold of pin T3 signal.

    Does the following describe about input signal's threshold?

    https://www.ti.com/lit/ds/symlink/omap-l137.pdf

    If the voltage of pin T3 is above 1.65V then it's detected as HIGH?

    And, if the voltage of pin T3 is under 1.65V then it's detected as LOW?

    Thanks and Best regards,

    Tsurumoto.

  • Hi Tsurumoto-san,

    The voltage range 1.827V to 1.457V falls between VIH(2V) and VIL(0.8V). The input buffer can become damaged if this condition remains for some period of time.

    From the above voltage results,  how was the transistor for internal pull-down working?

    It appears that the "strength" of the IPD transistor is about the same as the external 10k pull-up resistor, resulting in contention on the input voltage. The IPD transistor is fighting against the external pull-up IPD tries to pull the input voltage down while the external pull-up tries to pull the voltage up.

    Question: Does driving the pin as an output (logic high) result in a voltage greater than 2V? I recommend software drive this pin as an output to prevent damage caused by both PMOS and NMOS transistors being partially "ON" in the CMOS input buffer.

    Does the following describe about input signal's threshold?

    If the voltage of pin T3 is above 1.65V then it's detected as HIGH?

    And, if the voltage of pin T3 is under 1.65V then it's detected as LOW?

    No, Figure 6-2. states that the datasheet timing requirements and switching characteristics are measured from the time when the signal crosses Vref (50% of VDD) instead of some other point in time like when the signal crosses 10%/90% of VDD or the VIL/VIH thresholds. This defines the timing measurements only. It does not define the voltage input requirements.

    For example Setup time, AFSX0 input to ACLKX0 external input is measured from the time where AFSX0 crosses Vref (50% of VDD) until the time where ACLKX0 crosses Vref (50% of VDD). It does not mean that the signal is latched as a logic high or low when it crosses Vref (50% of VDD) - the signal must be above VIH or below VIL to be latched as a high or low.

    The input signals are defined as logic low or logic high if the signal is less than VIL or greater than VIH. Any voltage between these VIL/VIH are undefined. There is also hysteresis to prevent toggling (input changing states) between logic high and logic low while the input voltage is transitioning through the region between VIH and VIL.
    See 5.3 Recommended Operating Conditions
    VIH    High-level input voltage, I/O, 3.3V    = 2V (min)
    VIL    Low-level input voltage, I/O, 3.3V = 0.8V (max)
    VHYS Input Hysteresis = 160 mV (nominal)

    Regards,
    Mark

  • Hi Mark

    Thank you so much!

     

    >If the voltage is between VIL (0.8V) and VIH (2V) due to contention with IPD and external 10k pull-up,

    >this condition may lead to reliability issues before the device reaches its Recommended Power-On Hours.

    >We would need to reach out to the quality team to learn the maximum time this device can tolerate the mid-supply voltage at

    >an input buffer. And to understand the extend of the potential damage. I will ask if damage should be limited to that IO cell or more broad.

    Did you get any feed back from quality team about POH?

    The number of floating IOs and floating period may affect to assumption of POH,  then I would like to share the following information also.

    Customer found another 10 more IOs are also floating.

    One pin T3:  Enabled internal pull-down and external 10k pull-up. The signal is floating all the time.

    10 pins: Enabled internal pull-up and external pull-down. The signal is floating for 1.3 seconds just after device boot.

    Thanks and Best regards,

    Tsurumoto.

  • Tsurumoto-san,

    The quality team has been informed and is looking into this. I will give an update next week.

    Regards,
    Mark

  • Hi Mark

    Do you have any update?

  • Tsurumoto-san,

    Sorry for delayed response.

    The QRE team stated that driving inputs at mid rail is indeed expected to result in elevated reliability hazard due to crowbar current (both PMOS and NMOS partially on). Cumulative electro-migration damage will occur consistent with crowbar current.

    One pin T3:  Enabled internal pull-down and external 10k pull-up. The signal is floating all the time.

    10 pins: Enabled internal pull-up and external pull-down. The signal is floating for 1.3 seconds just after device boot.

    They stated that the T3 failure risk will be dire. The other pins will depend on the number of boots and cumulative exposure time to the crowbar current.

    To quantify the reliability hazard a lengthy exercise of SPICE simulation and analysis is necessary. This requires buy-in from the BU design team and program management. The customer would need to escalate the issue through proper channels.

    Regards,
    Mark

  • Hi Mark

    What does "buy-in " means? I'm not familiar with the word.

  • Tsurumoto-san,

    It just means that the BU needs to approve the resources to pursuit the exercise of quantifying the POH and failure rate.

    The T3 pin, which is always at a mid-supply voltage in this design, will suffer damage due to electro-migration. Simulation and analysis could tell us how quickly it will be damaged.

    For the other pins that float for 1.3 seconds after device boot, it depends on the cumulative time spent in this state over the life of the device. This is a factor of how many times the board is reset (and the input is at mid-supply voltage, causing electro-migration).

    The BU management needs to approve this simulation and analysis effort through some sort of escalation on your behalf.

    Regards,
    Mark