TDA4VM: The cortex r5f core executes coprocessor instructions, and the execution time is 105us

Hi,

The time seems large to me too. Can you see if there is no optimization compiler optimization happening in the code which may be stuffing more instructions in that window of GPIO high to low? Can you build the application in debug mode?

Regards,

Karan

hi Karan:

Thank you for your reply.

Let me describe the application I developed using MPU:

I am implementing memory protection of task / interrupt stack in AUTOSAR OS based on MPU unit of cortex-r5f.           

For example, OS is performing tasks in 10ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00000, sizeregval: 1KB, accessctrlregval: readable and writable           

 For example, OS is performing tasks of 1ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00400, sizeregval: 1KB, accessctrlregval: readable and writable           

For example, OS is performing tasks of 5ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00800, sizeregval: 1KB, accessctrlregval: readable and writable

FIgure 1  mcusw/build/j721e/mcu1_0/linker_r5.lds

FIgure 2   mcusw/build/j721e/mcu1_0/linker_r5.lds

Figure 3.  const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]

Hi,

yan gang said:

I am implementing memory protection of task / interrupt stack in AUTOSAR OS based on MPU unit of cortex-r5f.           

For example, OS is performing tasks in 10ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00000, sizeregval: 1KB, accessctrlregval: readable and writable           

 For example, OS is performing tasks of 1ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00400, sizeregval: 1KB, accessctrlregval: readable and writable           

For example, OS is performing tasks of 5ms cycle, and I call CSL_ Armr5mpucfgregion function, parameter regionnum: 10, baseaddrregval: 0x97c00800, sizeregval: 1KB, accessctrlregval: readable and writable

Should the MPU configuration not happen in the startup code before you run these runnable tasks? Something like _enable_mpu() in <SDK>/pdk*/packages/ti/csl/arch/r5/src/startup/startup.c?

All the regions in the MPU can be programmed in one go.

Karan Saxena said:

Can you see if there is no optimization compiler optimization happening in the code which may be stuffing more instructions in that window of GPIO high to low? Can you build the application in debug mode?

Also, is there a way for you to build you application with less compiler optimizations?

Regards,

Karan

hi, Karan Saxena ：

Thank you for your reply.

Can you see if there is no optimization compiler optimization happening in the code which may be stuffing more instructions in that window of GPIO high to low? Can you build the application in debug mode?

         The compiler instruction of my current project is: make - s base_ project_ mcu2 BUILD_ PROFILE=debug -j8

         BUILD_ PROFILE The value of the profile variable is debug

         CSL_Armr5mpucfgregion function is assembly code, compiler optimization level should not affect the efficiency of this function

Should the MPU configuration not happen in the startup code before you run these runnable tasks? Something like _enable_mpu() in <SDK>/pdk*/packages/ti/csl/arch/r5/src/startup/startup.c?

All the regions in the MPU can be programmed in one go.

Startup. C call_ enable_ Mpu() function, gcslr5mpucfg code is

const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
{
    {
        /* Region 0 configuration: complete 32 bit address space = 4Gbits */
        .regionId         = 0U,
        .enable           = 1U,
        .baseAddr         = 0x0U,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 1U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = 0U,
        .memAttr          = 0U,
    },
    {
        /* Region 1 configuration: 128 bytes memory for exception vector execution */
        .regionId         = 1U,
        .enable           = 1U,
        .baseAddr         = 0x0U,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128B,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 2 configuration: 1MB KB MCU MSRAM */
        .regionId         = 2U,
        .enable           = 1U,
        .baseAddr         = 0x41C00000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,

#if defined (SOC_J721E) || defined (SOC_J7200)
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
#endif
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 3 configuration: 2 MB MCMS3 RAM */
        .regionId         = 3U,
        .enable           = 1U,
        .baseAddr         = 0x70000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,

#if defined (SOC_J721E)
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
#endif

#if defined (SOC_J7200)
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
#endif

        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 4 configuration: 2 GB DDR RAM */
        .regionId         = 4U,
        .enable           = 1U,
        .baseAddr         = 0x80000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
    {
        /* Region 5 configuration: 32 KB BTCM */
        /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers
           It can either be '0x0' or '0x41010000'. Application/Boot-loader shall
           take care this configurations and linker command file shall be
           in sync with this. For either of the above configurations,
           MPU configurations will not changes as both regions will have same
           set of permissions in almost all scenarios.
           Application can chose to overwrite this MPU configuration if needed.
           The same is true for the region corresponding to ATCM. */
        .regionId         = 5U,
        .enable           = 1U,
        .baseAddr         = 0x41010000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
    {
        /* Region 7 configuration: 32 KB ATCM */
        .regionId         = 6U,
        .enable           = 1U,
        .baseAddr         = 0x0,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
        .memAttr          = 0U,
    },
    {
        /* stack */
        .regionId         = 9U,
        .enable           = 1U,
        .baseAddr         = 0x97c00000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_16KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },

     {
        /* init stack */
        .regionId         = 10U,
        .enable           = 1U,
        .baseAddr         = 0x97c02c00,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1KB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)FALSE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },
};

Now can you confirm that the execution time of armr5mpucfgregion function interface is 100US? Please test the execution time of armr5mpucfgregion function interface. The execution time is too long to meet the task scheduling time after adding memory protection. I hope to get help from experts