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AM6442: About GPMC error of TMDS64GPEVM evaluation board

tomitama
Expert 1090 points
Part Number: AM6442

The initial value of GPMC_CONFIG1_i [DEVICETYPE] is "0h: NOR flash-like".
GPMC_NAND_COMMAND_i resulted in an error when running the TMDS64GPEVM evaluation board with GPMC defaults.

(1) Why does a NAND error occur even though DEVICETYPE is the default NOR?
(2) Please tell me the setting value that does not cause GPMC error on the TMDS64GPEVM evaluation board.

==GPMC register of TMDS64GPEVM evaluation board==
--GPMC initial value
  GPMC_CONFIG1: 00000000h (CS1-3 is 00001000h)
  GPMC_CONFIG2: 00101001h
  GPMC_CONFIG3: 22060514h
  GPMC_CONFIG4: 10057016h
  GPMC_CONFIG5: 010F1111h
  GPMC_CONFIG6: 8F070000h
  GPMC_CONFIG7: 00000F40h (CS1-3 is 00000F00h)

--GPMC error register
  GPMC_ERR_TYPE [ERRORVALID]: 1h
  GPMC_ERR_TYPE [ERRORNOTSUPPADD]: 1h
  GPMC_ERR_TYPE [ILLEGALMCMD]: 2h
  GPMC_ERR_ADDRESS: 7B00013Ch (*)
    (*) A30   : 1h = for GPMC register region
        A29-0: 3B00013Ch = GPMC_NAND_COMMAND_i

  • 0
    Expert 1090 points

    Part Number: AM6442

    (1) When GPMC_ERR_TYPE [ERRORVALID] is 1h, is there a case where all of (a)-(c) are 0h?
        (a) GPMC_ERR_TYPE [ERRORNOTSUPPADD]
        (b) GPMC_ERR_TYPE [ERRORNOTSUPPMCMD]
        (c) GPMC_ERR_TYPE [ERRORTIMEOUT]

    (2) For example, if "3" is set for GPMC_CONFIG1_i [DEVICESIZE] (0: 8bit, 1: 16bit, 2: 32bit), which of (a)-(c) will be 1h?

    (3) Which of (a)-(d) is the timing when GPMC_ERR_TYPE [ERRORVALID] becomes 1h when an invalid value is written to the GPMC register?
        (a) When the GPMC register is written.
        (b) When GPMC_CONFIG7_i [CSVALID] is enabled after (a).
        (c) When accessing the GPMC memory space (0x50000000h-0x57FFFFFF) after (b).
        (d) Other than (a)-(c).

  • +1 in reply to tomitama
    TI__Mastermind 29270 points

    Hi,

    tomitama said:
    (1) When GPMC_ERR_TYPE [ERRORVALID] is 1h, is there a case where all of (a)-(c) are 0h?
        (a) GPMC_ERR_TYPE [ERRORNOTSUPPADD]
        (b) GPMC_ERR_TYPE [ERRORNOTSUPPMCMD]
        (c) GPMC_ERR_TYPE [ERRORTIMEOUT]

    (CORRECTED) I expect at least one of these bits should be set when ERRORVALID is 1. Or ERRORVALID should be 0 and none of the bits are set. I will check with the designer.

    This bit must be cleared by writing 1h. After writing 1h to clear it, does the bitfield read 1h again (with all other bitfields 0)? Does this condition only occur when GPMC_CONFIG1_i [DEVICESIZE] = 2: 32bit?

    tomitama said:
    (2) For example, if "3" is set for GPMC_CONFIG1_i [DEVICESIZE] (0: 8bit, 1: 16bit, 2: 32bit), which of (a)-(c) will be 1h?

    GPMC_CONFIG1_i [DEVICESIZE] should not cause any of these GPMC_ERR_TYPE bitfields to be set to 1h. Ca

    tomitama said:
    (3) Which of (a)-(d) is the timing when GPMC_ERR_TYPE [ERRORVALID] becomes 1h when an invalid value is written to the GPMC register?
        (a) When the GPMC register is written.
        (b) When GPMC_CONFIG7_i [CSVALID] is enabled after (a).
        (c) When accessing the GPMC memory space (0x50000000h-0x57FFFFFF) after (b).
        (d) Other than (a)-(c).

    I believe the GPMC_ERR_TYPE register gets set (c) when accessing the GPMC memory space, if there is some issue to cause the error.
    Could you share the GPMC register dump and specify which address in the GPMC memory space was read or written to?

    Regards,
    Mark

  • +1
    TI__Guru** 114410 points

    Can you please indicate what software is being used in your test. As far as I know, we are currently not supporting any driver for GPMC.

    Regards,

    Rahul

  • +1
    TI__Mastermind 29270 points

    Now that I see the GPMC_CONFIG registers. I checked them, and the timings look okay.

    Try GPMC_CONFIG7 = 0x00000F50 instead of 0x00000F40 (for base address 0x50000000 on AM642x - GPMC_CONFIG7_n [5:0] BASEADDRESS is changed).

    Also use unique BASEADDRESS values for CS1-3.

    GPMC_CONFIG7_n [5:0] BASEADDRESS correspond to A29, A28, A27, A26, A25, and A24 of the system address (within GPMC data memory map) that you want CSn to be used with. This BASEADDRESS bit field combined with MASKADDRESS bit field determine the memory mapping of the system addresses to each CSn (as configured by the GPMC_CONFIGm_n registers).

    Multiple chip selects must not be configured to respond to the same BASEADDRESS.

    For example CS0 might start at 0x50000000,GPMC_CONFIG7_0 = 0x00000F50
    CS1 might start at 0x51000000, GPMC_CONFIG7_1 = 0x00000F51
    CS2 might start at 0x52000000, GPMC_CONFIG7_1 = 0x00000F52

    To clarify, in system address 0x52000000 bits[29:24] = 0b010010, so GPMC_CONFIG7_n [5:0] BASEADDRESS = 0b010010 (12h).
    Maybe the error will go away.

    Regards,
    Mark