Other Parts Discussed in Thread: AM3358,
Dear TI experts,
I'm currently migrating from a design based on AM3358 to one based on the newest family AM64x (in detail AM6441), and I'm facing a problem related to the ETH interface section.
In the previous design I interconnected ETH PHYs through MII interface (allowed by AM3358), but now it seems that AM64 Sitara processor family allows only RGMII or RMII interfaces, but NOT the MII one. Is this correct?
To support this theory I found out (in the datasheet) that AM6441 pins only refer to RGMII_xxx or RMII_xxx:
After that, I read also the AM64x TRM and I found this PRU_ICSSG section, which instead refers to MII ports:
So, the question is "Is MII interface supported even in AM64x processor family or not"? And if the answer is YES, which are the pins to be connected with ETH PHYS for a complete MII setup? RMII_xxx pins are only two (RXD0/RXD1 and TXD0/TXD1), so it seems they are not the right ones...
Thank you in advance for your help.
Flavio