TDA4VM: SERDES PHY LAYERS INTERFACE

yutai li

Intellectual 620 points

Part Number: TDA4VM

Hi TI Support Team

I want to double check with you about the TDA4 serdes physical layers interface.

Because PCIe / USB / SGMII / DP share same serdes in TDA4.

when we use SGMII from Serdes,

1. Do you know if it is CML I/O for TDA4 SGMII interface ? Which buffer in Serdes LVDS or CML or others IO?

2. Do we need enable TDA4 RX internal termination from SW ? which register can change it.

3. Do we need enable pre-emphasis in default from SW? which register can change it.

Currently our design ad below:

TDA4 TX ( which buffer ???) ====AC(100nF/0402)=======>PHY (CML I/O input / internal 100ohm input impedance)

TDA4 RX ( which buffer ???) <====AC(100nF/0402)=======PHY (CML I/O output)

Some confuse about the TDA4 TX test waveform.

1. The level high and low in highlight area don't same as others level.

2. Does is cause by pre-emphasis from TDA4?

3. Does it is correct waveform ? Do you have your EVM test waveform for SGMII interfac. We can compare with us.

Thanks

Yutai

over 2 years ago

0 ShreyasRao over 2 years ago

TI__Guru 55970 points

Yutai,

Most of the questions are available in the TDA4VM Technical reference manual (User Guide) which also has register setting information for all interfaces included.

https://www.ti.com/product/TDA4VM

SGMII uses CML and you need AC caps as you have mentioned.

The waveform doesn't look right to me, we get a clean eye for the SGMII. Do you have the termination correctly set and have the de-embedding done?

0 yutai li over 2 years ago in reply to ShreyasRao

Intellectual 620 points

Hi TI Expert

Which register we can used to enable pre-emphasis and de-emphais. I don't find it in TRM.

I have double check with Marvell FAE, The ETH Phy side have internal termination in CML.

So i have confuse about the test result. I guess it came from the pre-emphasis but i can not find the register.

Thanks

Yutai

0 ShreyasRao over 2 years ago in reply to yutai li

TI__Guru 55970 points

Yutai,

I will have to check this with my internal S/W team and will have to let you know.

0 ShreyasRao over 2 years ago in reply to ShreyasRao

TI__Guru 55970 points

Yutai,

referring to the other e2e post here about the SGMII de-emphasis from the s/w team.

"There was a finding while running SGMII char that the TX swing/amplitude was not high enough and some registers in the serdes were updated. It looks like the CSL libraries are still pointing to the older setting. I will make an update to the CSL serdes configuration for SGMII and release it." I am told that it would be worked on by the end of the month.

0 ShreyasRao over 2 years ago in reply to ShreyasRao

TI__Guru 55970 points

Yutai,

referring to the other e2e post here below which the s/w apps engineer is working.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1019099/tda4vm-sgmii-de-emphasis-register/3767168#3767168

0 yutai li over 2 years ago in reply to ShreyasRao

Intellectual 620 points

Hi Shreyas Rao

We are using the default config from your PKD, csl_wiz16m_cs_refclk100MHz_20b_SGMII.c

Can you share the interim patch to us ?

Thanks

Yutai

0 ShreyasRao over 2 years ago in reply to yutai li

TI__Guru 55970 points

Yutai,

Understand. I would have to defer to the s/w apps support for this, who develop and support the CCS aspect. I have already sent out an email to him about this and will let you know once I receive anything. I am told that by the end of the week is targeted for the patch release.

0 ShreyasRao over 2 years ago in reply to ShreyasRao

TI__Guru 55970 points

/cfs-file/__key/communityserver-discussions-components-files/791/csl_5F00_wiz16m_5F00_cs_5F00_refclk100MHz_5F00_20b_5F00_SGMII.c

interim file patch received referring to the other e2e post.

let us know if it solves the issue.

0 yutai li over 2 years ago in reply to ShreyasRao

Intellectual 620 points

Hi Shreyas Rao

I have use your patch, but it don't fix this issue.

I also find other thread in E2E. Look like we meet same issue.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1019099/tda4vm-sgmii-de-emphasis-register/3767168#3767168

Thanks

Yutai

0 ShreyasRao over 2 years ago in reply to yutai li

TI__Guru 55970 points

Yutai,

Yes, here is the SGMII de-emphasis register as you had required.

0 ShreyasRao over 2 years ago in reply to ShreyasRao

TI__Guru 55970 points

Also, I noted that the characterization was done on the SGMII using the 156.25Mhz ref clk and you are likely using the 100Mhz ref clk. You may have to play around with the reg values to get this to work. Here are the values used for the 156.25Mhz ref clk.

DRVCTRL_AMPBOOST_TUNE_PREG = 0x7

DRVCTRL_EDGEBOOST_TUNE_PREG =0x2

CMN_RESCAL_TXOFFSET_PREG=0x27

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TDA4VM: SERDES PHY LAYERS INTERFACE