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[FAQ] TDA4VM: How to configure 4266MTS DDR on 7.2 SDK

jiang dong
Prodigy 100 points
Part Number: TDA4VM

Hi，

I use yocto to compile mc:k3r5:u-boot-ti-staging to generate the tiboot3.bin file, and then use the SD boot method. But I found that when using the 7.2 version of tiboot3.bin, the ddr frequency is 3200M, but when using the 7.3 version of tiboot3.bin, the ddr frequency is 4266M. I have not found the difference in the ddr frequency settings between the two versions. Can you tell me? Thank you！

BR,

Jordon

  • 0
    Prodigy 100 points

    Using version 7.2, how to increase the ddr frequency to 4266M? Tks!

  • +1 in reply to jiang dong
    TI__Guru*** 130860 points

    Hi Jiang dong,

    You are correct. The intended frequency of DDR on SDK 7.2 was also 4266M.
    Due to a bug in the divider computation the frequency was inadvertently configured to 3200M.

    This was fixed on SDK 7.3 with the following patches on u-boot.

    ddr-clk-divider.zip

    Just unzip the file in the u-boot directory.

    git am ddr-clk-divider/*
    cd ../..
    make u-boot

    cp board-support/u-boot_build/a72/u-boot.img board-support/u-boot_build/a72/tispl.bin board-support/u-boot_build/r5/tiboot3.bin /media/$USER/boot

    Here are the results for DDR_PLL Clock before applying patches on 7.2:

    k3conf dump clock 47 2

    |---------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |---------------------------------------------------------------------------------------|
    | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
    | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 799876923 |
    | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
    | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
    | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
    |---------------------------------------------------------------------------------------|

    After:

    k3conf dump clock 47


    |---------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name | Status | Clock Frequency |
    |---------------------------------------------------------------------------------------|
    | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 |
    | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
    | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 |
    | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 |
    | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 |
    | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 |
    |---------------------------------------------------------------------------------------|

    The calculation for DDR frequency is DDR_PLL_CLK * 4 = 1066 * 4 = 4266M.

    Please click on verify answer If you can reproduce the above behavior.

    Best Regards,
    Keerthy