Hello.
It's a poor English sentence, but please keep in touch.
I have already asked a question to the TI Customer Center in Japan.
I have a question about the relationship between the optimization level and Flash ROM boot.
Target device: TMS320C6726
Boot device: Parallel Flash ROM
Migrate the environment of CCS3.3 + FlashBurn to CCS7 + original FlashWriter.
First of all, I understand that the flow of "boot ==> _c_int00 ==> main" is as follows.
At the 1st boot, the 0x400 bytes at the beginning of the Flash ROM are read to the DSP internal RAM, and the actual 2nd boot (copy) is performed.
In the 2nd boot, place (copy) the following.
0x80000320 _c_int00
0x802700c0 _main
(Both are placed in SDRAM)
When the 2nd boot is completed, it will enter (branch) to _c_int00, jump to main, and then the farm will be executed.
◆ Problem:
Operation from FlashROM boot is possible at optimization level = Disable, but operation from FlashROM boot is not possible at optimization level = 2.
◆ Confirmation details:
Read pulse (CS2 or RD signal) from FlashROM at the timing of 1st boot,
At the timing of 2nd boot, the read pulse (CS2 and RD signal) from FlashROM and
Check the write pulse (CS, WR signal, etc.) to SDRAM.
* I expect that you may not be able to branch from 2nd boot to _c_int00 or from _cint00 to main.
◆ Question 1:
When compiling with optimization level = Disable (Debug mode), when compiling with optimization level = 2 (Release mode),
Is there a timing difference in the flow of "boot ==> _c_int00 ==> main"?
◆ Question 2:
If there is a difference in Question 1 above, does it cause a malfunction?
Is there any way to deal with the problem?
Let me borrow your wisdom.
Thank you.