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Part Number: TMDXIDK5718
Other Parts Discussed in Thread: AM5718


TMDXIDK5718 Circuit diagram There is a description of the connection circuit diagram of AM5718 and DDR on page 8.

The block diagram of TMDXIDK5718 says "DDR3 1GB". Why are three 512MB DDR3s installed?

Another question is that the data bus connection is different, such as DDR_D4 connecting to DQ2. Why?


  • Hi, 

    Component "U6" in schematic "AM571x_INDUSTRIAL_EVM_3M0000_PDF_REF1_3A.pdf" is connected to the DDR ECC pins of AM571x, and thus are used for ECC and not data storage. 

    AM5718 can support DDR bit swapping (within a byte lane) when interfaced to DDR3 since the DQ lines are not used for other functions outside of the data value. Thus, it doesn't matter if the data is swapped during a write as it will (effectively) be un-swapped during the read. One might swap the signals for easier routing.