• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 102 subscribers
  • Views 235 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6674: IBIS Model Selector and DSP Settings

O.H
Genius 5350 points
Part Number: TMS320C6674
Other Parts Discussed in Thread: TMS320C6678

Hi experts,

For the IBIS model of the C6674, when the following is selected, please tell me how to set the DSP side. The following is an excerpt from the file "tms320C6678_4_2_1_r1p5b.ibs".

|************************************************************************************
[Model Selector] bshtltcscddvgpbfz
|bshtltcscddvgpbfzDriver Positive Pad
| bshtltcscddvgpbfz.ibs [15July2011 revision 1.1]
|************************************************************************************
|
CSCDDVGPBFZ_FAST_8MA_5PER_P TX 50 ohms Fast (SR0 1; SR1 0)

  • CSCDDVGPBFZ_FAST_8MA_5PER_P
    • What does this part mean? If it is related to what should be set on the DSP side, what documents should I refer to?

  • TX 50 ohms
    • I understand that I need to set "SDRAM_DRIVE" in SDRAM Configuration Register (SDCFG).(Refer to Keystone Architecture DDR3 Memory Controller (Rev. E):Table 4-5. SDRAM Configuration Register (SDCFG) Field Descriptions). However, the RZQ register is 240 ohms, so can you tell me how to set it to 50 or 45 ohms?

  • Fast (SR0 1; SR1 0)
    • I understand that the slew rate can be selected as Fast by setting DDRSLRATE0 and 1 from the table below. (Refer to Hardware design guide for KeyStone devices (Rev. D):6.8.3 Slew Rate Control 

Best regards,
O.H

  • 0
    Genius 5350 points

    Hello,

    I'm sorry to rush you. What is the situation?

    The customer needs answers, so it would be helpful if you could share your progress with us.

    Best regards,
    O.H

  • 0
    TI__Mastermind 46712 points

    Hello OH,

    A few docs of interest: 

    KeyStone I DDR3 Initialization (Rev. E)

    DDR3 Design Requirements for KeyStone Devices (Rev. C)

    DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)

    To your questions ... 

    The CSCDDVGPBFZ is the library name for the particular IO buffer used inside the SoC for the DDR differential IOs.  They are mapped to (for example) the dqs0n and dqs0p pins.

    The remainder of this string: _FAST_8MA_5PER_P ... is fairly arbitrary, but the FAST / FASTEST / SLOW / SLOWEST maps to the SR1:0 settings that you mention.  The 5PER_P can be ignored.

    The 8mA/9mA/10mA maps is effectively the drive strength.  It maps to the 50/45/40 settings that can be programmed with the SDRAM_DRIVE parameter.  

    If you refer to the DDR3 Initialization appnote,  Table 3. SDRAM Configuration Register Values SDRAM_DRIVE is recommended at 0x1=RZQ/7 which is effectively 34 Ohms i.e., the "strongest" buffer available.  In that case I would recommend the 10mA / 40 Ohm configuration for the IBIS model.

    And the Hardware Design Guideline appnote,  6.8.3 Slew Rate Control states that " For normal full speed operation, the DDRSLRATE pins should be pulled low".  This maps to FASTEST.

    In summary, you should use the model named CSCDDVGPBFZ_FASTEST_10MA_5PER_P.

    Regards,

    Kyle