Other Parts Discussed in Thread: REG102, REG101,
Hello,
I am trying to test the McASP tx in polling mode.
I am builing it over the example specified in the following pdk path:
PROCESSOR_SDK_VISION_03_08_00_00/ti_components/drivers/pdk_01_10_04_05/packages/ti/drv/stw_lld/examples/mcasp/mcasp_sinetone
This example is transmitting a sine wave from Memory to EDMA then to Mcasp then to codec, I modified it to work in polling mode depending on"Table 26-408" and "Figure 26-126" sections specified in the following document :
https://www.ti.com/lit/ug/spruif0c/spruif0c.pdf
The modified code is:
/******************************************************************************
* INCLUDE FILES
*******************************************************************************/
#include <stdint.h>
#include <stddef.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/csl_types.h>
#include <ti/drv/stw_lld/uartconsole/uartStdio.h>
#include <ti/drv/stw_lld/examples/utility/stwutils_app.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/csl_mcasp.h>
#include <ti/drv/stw_lld/i2clld/lld_hsi2c.h>
#include <ti/drv/stw_lld/platform/platform.h>
#if (defined (__ARM_ARCH_7A__) || defined (_TMS320C6X))
#include <ti/drv/stw_lld/platform/irq_xbar.h>
#endif
#include "audio_codec.h"
/******************************************************************************
** INTERNAL MACRO DEFINITIONS
******************************************************************************/
/* Change MACRO DEBUG to 1 in case for checking I2C read and write values */
#define DEBUG (0)
#define SOC_MCASP_3_FIFO_REGS (SOC_MCASP3_CFG_BASE + 0x1000)
/*
** Values which are configurable
*/
/* Slot size to send/receive data */
#define SLOT_SIZE (32U)
/* Word size to send/receive data. Word size <= Slot size */
#define WORD_SIZE (32U)
/* Number of channels, L & R */
#define NUM_I2S_CHANNELS (2U)
/* Number of serializer */
#define NUM_OF_SERIALIZER (1U)
/* Number of samples to be used per audio buffer */
#define NUM_SAMPLES_PER_AUDIO_BUF (96U)
/* Specify where the parameter set starting is */
#define PAR_ID_START (72U)
/* McASP Serializer 0 for Transmit */
#define MCASP_XSER_TX_0 (0U)
/*
** Below Macros are calculated based on the above inputs
*/
#define I2S_SLOTS ((1 << NUM_I2S_CHANNELS) - 1)
#define BYTES_PER_SAMPLE ((WORD_SIZE >> 3) \
* NUM_OF_SERIALIZER)
#define AUDIO_BUF_SIZE (NUM_SAMPLES_PER_AUDIO_BUF \
* BYTES_PER_SAMPLE)
#define PAR_TX_START (PAR_ID_START)
/*
** EMDA paRAM set size
*/
#define SIZE_PARAMSET (32U)
/*
** Definitions which are configurable depending on the application requirement
*/
#define MCASP_ACLKX_CLKXDIV_VALUE (0x6U)
#define MCASP_AHCLKX_HCLKXDIV_VALUE (0x9U)
/*
** Audio Codec I2C slave address
*/
#if defined (SOC_TDA2EX)
#define AUDIO_CODEC_SLAVE_ADDR (0x19)
#else
#define AUDIO_CODEC_SLAVE_ADDR (0x19)
#define AUDIO_CODEC_SLAVE_ADDR_1 (0x18)
#endif
#define GPIO_IO_EXPANDER_SLAVE_ADDR (0x26)
/*
** EDMA completion interrupt number
*/
#define EDMA3_CC_XFER_COMPLETION_INT_A15 (12U)
#define EDMA3_CC_XFER_COMPLETION_INT_DSP (38U)
#ifdef __ARM_ARCH_7A__
#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_A15
#elif defined _TMS320C6X
#define EDMA3_CC_XFER_COMPLETION_INT EDMA3_CC_XFER_COMPLETION_INT_DSP
#endif
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00FF0000U)
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000010U)
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000U)
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x000000FFU)
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000U)
#define INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000U)
#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (230U)
#define EDMA3_EVENT_MUX_REG_BASE_ADDR (0x4a002c78)
/*
** Definitions which are configurable depending on the core to be used
*/
#define EDMA3_CHA_MCASP3_TX (5)
#define EDMA3_CC_REGION_A15 (0U)
#define EDMA3_CC_REGION_DSP (2U)
#define EDMA3_CC_QUEUE (0U)
#define MCASP3_RX_DMA_XBAR_INST (132U)
#define MCASP3_TX_DMA_XBAR_INST (133U)
#define I2S_MODE (2U)
/******************************************************************************
** STRUCTURE DEFINITIONS
******************************************************************************/
typedef struct {
volatile unsigned int TPCC_EVTMUX[32];
} IntmuxRegs;
/******************************************************************************
** INTERNAL FUNCTION PROTOTYPES
******************************************************************************/
static void EDMA3IntSetup(void);
static void EDMA3CCComplIsr(void *dummy);
/*I2C Init*/
void i2c_init(LLD_Hsi2cInstId_t instId);
/*I2C De-Init*/
void i2c_deinit();
LLD_hsi2cErrorCode_t I2CWrite(uint8_t address, uint8_t data);
LLD_hsi2cErrorCode_t I2CWrite1(uint8_t address, uint8_t data);
LLD_hsi2cErrorCode_t I2C_Read(uint8_t address, uint8_t *data);
LLD_hsi2cErrorCode_t I2CWriteBf(uint8_t regAddr, uint8_t bfPosition,
uint8_t bfSize,
uint8_t bfData);
/*Dac Init*/
static void aic31InitDac();
/*Codec Init*/
static void aic31MdCreateChan();
static LLD_hsi2cErrorCode_t updateAudioCodecAddr(void);
/******************************************************************************
** INTERNAL VARIABLE DEFINITIONS
******************************************************************************/
typedef volatile IntmuxRegs *IntmuxRegsOvly;
/* I2C transfer buffer */
uint8_t data_tx[4];
/* I2C Receive buffer */
uint8_t data_rx[4];
int16_t _sineWavePattern[] =
{
0x0000, 0x0000, 0x10b4, 0x10b4, 0x2120, 0x2120, 0x30fb, 0x30fb, 0x3fff,
0x3fff, 0x4dea, 0x4dea, 0x5a81, 0x5a81, 0x658b, 0x658b,
0x6ed8, 0x6ed8, 0x763f, 0x763f, 0x7ba1, 0x7ba1, 0x7ee5, 0x7ee5, 0x7ffd,
0x7ffd, 0x7ee5, 0x7ee5, 0x7ba1, 0x7ba1, 0x76ef, 0x76ef,
0x6ed8, 0x6ed8, 0x658b, 0x658b, 0x5a81, 0x5a81, 0x4dea, 0x4dea, 0x3fff,
0x3fff, 0x30fb, 0x30fb, 0x2120, 0x2120, 0x10b4, 0x10b4,
0x0000, 0x0000, 0xef4c, 0xef4c, 0xdee0, 0xdee0, 0xcf06, 0xcf06, 0xc002,
0xc002, 0xb216, 0xb216, 0xa57f, 0xa57f, 0x9a75, 0x9a75,
0x9128, 0x9128, 0x89c1, 0x89c1, 0x845f, 0x845f, 0x811b, 0x811b, 0x8002,
0x8002, 0x811b, 0x811b, 0x845f, 0x845f, 0x89c1, 0x89c1,
0x9128, 0x9128, 0x9a76, 0x9a76, 0xa57f, 0xa57f, 0xb216, 0xb216, 0xc002,
0xc002, 0xcf06, 0xcf06, 0xdee0, 0xdee0, 0xef4c, 0xef4c
};
/*
** McASP transmit buffers.
*/
static uint8_t txBuf0[AUDIO_BUF_SIZE];
/*
** I2C instance zero handle
*/
hsI2cHandle i2cHandle;
/*
** I2C instance one handle
*/
hsI2cHandle i2cHandle1;
uint8_t audioCodecSlaveAddr = (uint8_t) AUDIO_CODEC_SLAVE_ADDR;
/******************************************************************************
** INTERNAL CONSTATNT DEFINITIONS
******************************************************************************/
/*
** Default paRAM for Transmit section. This will be transmitting from
** a loop buffer.
*/
static EDMA3CCPaRAMEntry const txDefaultPar = {
(uint32_t) EDMA3CC_OPT_TCC_SET(EDMA3_CHA_MCASP3_TX),
(uint32_t) txBuf0, /* source address */
(uint16_t) (4), /* aCnt */
(uint16_t) (AUDIO_BUF_SIZE / 4), /* bCnt */
(uint32_t) (SOC_MCASP3_BASE), /* dest address */
(uint16_t) (4), /* source bIdx */
(uint16_t) (0), /* dest bIdx */
(uint16_t) (PAR_TX_START * SIZE_PARAMSET), /* link address */
(uint16_t) (1), /* bCnt reload value */
(uint16_t) (0), /* source cIdx */
(uint16_t) (0), /* dest cIdx */
(uint16_t) (1) /* cCnt */
};
/******************************************************************************
** FUNCTION DEFINITIONS
******************************************************************************/
void McASPTxStatusPrint(uint32_t baseAddr)
{
uint32_t stat_val = 0U;
uint8_t XERR_bit = 0U;
uint8_t XDMAERR_bit = 0U;
uint8_t XSTAFRM_bit = 0U;
uint8_t XDATA_bit = 0U;
uint8_t XLAST_bit = 0U;
uint8_t XTDMSLOT_bit = 0U;
uint8_t XCKFAIL_bit = 0U;
uint8_t XSYNCERR_bit = 0U;
uint8_t XUNDRN_bit = 0U;
stat_val = McASPTxStatusGet(baseAddr);
XERR_bit = (stat_val & MCASP_TXSTAT_XERR_MASK) >> MCASP_TXSTAT_XERR_SHIFT;
XDMAERR_bit = (stat_val & MCASP_TXSTAT_XDMAERR_MASK) >> MCASP_TXSTAT_XDMAERR_SHIFT;
XSTAFRM_bit = (stat_val & MCASP_TXSTAT_XSTAFRM_MASK) >> MCASP_TXSTAT_XSTAFRM_SHIFT;
XDATA_bit = (stat_val & MCASP_TXSTAT_XDATA_MASK ) >> MCASP_TXSTAT_XDATA_SHIFT;
XLAST_bit = (stat_val & MCASP_TXSTAT_XLAST_MASK) >> MCASP_TXSTAT_XLAST_SHIFT;
XTDMSLOT_bit = (stat_val & MCASP_TXSTAT_XTDMSLOT_MASK) >> MCASP_TXSTAT_XTDMSLOT_SHIFT;
XCKFAIL_bit = (stat_val & MCASP_TXSTAT_XCKFAIL_MASK) >> MCASP_TXSTAT_XCKFAIL_SHIFT;
XSYNCERR_bit = (stat_val & MCASP_TXSTAT_XSYNCERR_MASK) >> MCASP_TXSTAT_XSYNCERR_SHIFT;
XUNDRN_bit = (stat_val & MCASP_TXSTAT_XUNDRN_MASK) >> MCASP_TXSTAT_XUNDRN_SHIFT;
UARTPuts("\r\n-------------TX status ------------ ", -1);
UARTPuts("\r\nXERR_bit ", -1);
UARTPutHexNum(XERR_bit);
UARTPuts("\r\nXDMAERR_bit ", -1);
UARTPutHexNum(XDMAERR_bit);
UARTPuts("\r\nXSTAFRM_bit ", -1);
UARTPutHexNum(XSTAFRM_bit);
UARTPuts("\r\nXDATA_bit ", -1);
UARTPutHexNum(XDATA_bit);
UARTPuts("\r\nXLAST_bit ", -1);
UARTPutHexNum(XLAST_bit);
UARTPuts("\r\nXTDMSLOT_bit ", -1);
UARTPutHexNum(XTDMSLOT_bit);
UARTPuts("\r\nXCKFAIL_bit ", -1);
UARTPutHexNum(XCKFAIL_bit);
UARTPuts("\r\nXSYNCERR_bit ", -1);
UARTPutHexNum(XSYNCERR_bit);
UARTPuts("\r\nXUNDRN_bit ", -1);
UARTPutHexNum(XUNDRN_bit);
UARTPuts("\r\n------------------------------------------", -1);
}
/* I2C instance Init */
void i2c_init(LLD_Hsi2cInstId_t instId)
{
lld_hsi2c_initParam_t initPar;
hsI2cObjHandle i2cObjHandle;
initPar.opMode = HSI2C_OPMODE_POLLED;
initPar.i2cBusFreq = I2C_NORMAL;
initPar.is10BitAddr = 0;
initPar.isMasterMode = 1;
lld_i2c_init(&i2cObjHandle, instId, &initPar);
if (HSI2C_INST_0 == instId)
{
i2cHandle = lld_i2c_open(instId, NULL, NULL);
}
#if (defined (SOC_TDA2XX) || defined (SOC_TDA2PX))
if (HSI2C_INST_1 == instId)
{
i2cHandle1 = lld_i2c_open(instId, NULL, NULL);
}
#elif (defined (SOC_TDA2EX))
if (HSI2C_INST_4 == instId)
{
i2cHandle1 = lld_i2c_open(instId, NULL, NULL);
}
#endif
}
/* I2C close and deinit */
void i2c_deinit()
{
lld_i2c_close(&i2cHandle);
lld_i2c_deinit(HSI2C_INST_0);
lld_i2c_close(&i2cHandle1);
#if (defined (SOC_TDA2XX) || defined (SOC_TDA2PX))
lld_i2c_deinit(HSI2C_INST_1);
#elif (defined (SOC_TDA2EX))
lld_i2c_deinit(HSI2C_INST_4);
#endif
}
/* I2C write function */
LLD_hsi2cErrorCode_t I2CWrite(uint8_t address, uint8_t data)
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
lld_hsi2c_datatfr_params_t i2cXferParams;
i2cXferParams.bufLen = 2;
i2cXferParams.buffer = &data_tx[0];
data_tx[0] = address;
data_tx[1] = data;
#if DEBUG
UARTPuts("\r\n i2c write: address : ", -1);
UARTPutHexNum(data_tx[0]);
UARTPuts(" data : ", -1);
UARTPutHexNum(data_tx[1]);
#endif
i2cXferParams.flags = LLD_HSI2C_WRITE | LLD_HSI2C_MASTER | LLD_HSI2C_START
| LLD_HSI2C_STOP;
i2cXferParams.slaveAddr = audioCodecSlaveAddr;
i2cXferParams.timeout = 0xFFFFFF;
retVal = lld_i2c_transfer(i2cHandle, &i2cXferParams);
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nI2c write failed ", -1);
}
#if DEBUG
else
{
UARTPuts("\r\nI2c write successful ", -1);
}
#endif
return retVal;
}
LLD_hsi2cErrorCode_t I2CWrite1(uint8_t address, uint8_t data)
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
lld_hsi2c_datatfr_params_t i2cXferParams;
hsI2cHandle ioexpi2cHandle;
i2cXferParams.bufLen = 2;
i2cXferParams.buffer = &data_tx[0];
data_tx[0] = address;
data_tx[1] = data;
#if DEBUG
UARTPuts("\r\n i2c write: address : ", -1);
UARTPutHexNum(data_tx[0]);
UARTPuts(" data : ", -1);
UARTPutHexNum(data_tx[1]);
#endif
i2cXferParams.flags = LLD_HSI2C_WRITE | LLD_HSI2C_MASTER | LLD_HSI2C_START
| LLD_HSI2C_STOP;
i2cXferParams.slaveAddr = (uint8_t) GPIO_IO_EXPANDER_SLAVE_ADDR;
i2cXferParams.timeout = 0x4000;
#if defined (SOC_TDA2PX)
/* For TDA2PX both io expander and the codec are on i2c0 */
ioexpi2cHandle = i2cHandle;
#else
ioexpi2cHandle = i2cHandle1;
#endif
retVal = lld_i2c_transfer(ioexpi2cHandle, &i2cXferParams);
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nI2c write failed ", -1);
}
#if DEBUG
else
{
UARTPuts("\r\nI2c write successful ", -1);
}
#endif
return retVal;
}
LLD_hsi2cErrorCode_t I2C_Read(uint8_t address, uint8_t *data)
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
lld_hsi2c_datatfr_params_t i2cXferParams;
i2cXferParams.bufLen = 1;
i2cXferParams.buffer = &data_tx[0];
data_tx[0] = address; /*address byte msb*/
i2cXferParams.flags =
LLD_HSI2C_WRITE | LLD_HSI2C_MASTER | LLD_HSI2C_START /*|
*LLD_HSI2C_STOP*/;
i2cXferParams.slaveAddr = audioCodecSlaveAddr;
i2cXferParams.timeout = 0xFFFFFF;
retVal = lld_i2c_transfer(i2cHandle, &i2cXferParams);
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nI2c write failed ", -1);
}
#if DEBUG
else
{
UARTPuts("\r\nI2c write successful ", -1);
}
#endif
i2cXferParams.buffer = &data_rx[0];
i2cXferParams.flags = LLD_HSI2C_READ | LLD_HSI2C_MASTER |
LLD_HSI2C_START | LLD_HSI2C_STOP |
LLD_HSI2C_IGNORE_BUS_BUSY;
retVal = lld_i2c_transfer(i2cHandle, &i2cXferParams);
#if DEBUG
UARTPuts("\r\n i2c read : address : ", -1);
UARTPutHexNum(data_tx[0]);
UARTPuts(" data : ", -1);
UARTPutHexNum(data_rx[0]);
#endif
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nI2c read failed ", -1);
}
#if DEBUG
else
{
UARTPuts("\r\nI2c read successful ", -1);
*data = data_rx[0];
}
#endif
return retVal;
}
LLD_hsi2cErrorCode_t I2CWriteBf(uint8_t regAddr, uint8_t bfPosition,
uint8_t bfSize,
uint8_t bfData)
{
uint8_t regData = 0; /* Temporary Register data */
uint8_t mask = 0; /* Bit field mask */
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
/*Read data from regAddr*/
retVal = I2C_Read(regAddr, ®Data);
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nI2c read failed ", -1);
}
mask = ((1 << bfSize) - 1) << bfPosition;
regData = (regData & (uint8_t) (~(mask)));
regData = (regData | (uint8_t) (bfData << bfPosition));
/* Write the modified data back into the register */
retVal = I2CWrite(regAddr, regData);
return retVal;
}
/**
*
* \brief This function writes the initialization values for Aic31 DAC
* registers. This function should be called to initialize the
* registers of the DAC.
*
* \return None
*/
static void aic31InitDac()
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
uint8_t gain = 0x24;
/* Write the initialization values for the DAC registers */
retVal = I2CWriteBf((uint8_t) Aic31_P0_REG7, (uint8_t) 1, (uint8_t) 4,
(uint8_t) 5);
/* power up the left and right DACs */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG37,
(uint8_t) 0xE0));
/* select the DAC L1 R1 Paths */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG41,
(uint8_t) 0x02));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG42,
(uint8_t) 0x6C));
/* unmute the DAC */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG43,
(uint8_t) 0x00));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG44,
(uint8_t) 0x00));
/* DAC L to HPL OUT Is connected */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG47,
(uint8_t) 0x80));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG51,
(uint8_t) 0x09));
/* DAC R to HPROUT is connected */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG64,
(uint8_t) 0x80));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG65,
(uint8_t) 0x09));
/* DACL1 connected to LINE1 LOUT */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG82,
(uint8_t) 0x80));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG86,
(uint8_t) 0x09));
/* DACR1 connected to LINE1 ROUT */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG92,
(uint8_t) 0x80));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG93,
(uint8_t) 0x09));
/* Left/Right DAC digital volume gain */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_LEFT_DAC_VOL_CTRL_ADDR,
/*(uint8_t) gain*/ gain));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t)
Aic31_RIGHT_DAC_VOL_CTRL_ADDR,
/*(uint8_t) gain*/ gain));
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nDAC Initialization failed ", -1);
}
else
{
UARTPuts("\r\nDAC Initialization successful", -1);
}
}
static void aic31MdCreateChan()
{
uint8_t tempData = 0;
uint8_t pllPValue = 0;
uint8_t pllRValue = 0;
uint8_t pllJValue = 0;
uint8_t pllDLowValue = 0;
uint8_t pllDHighValue = 0;
uint8_t dualRate = 0;
uint8_t sampleRateDiv = 0;
uint8_t fsRef = 0;
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
/* Select Register Page 0 of Aic31 */
retVal = I2CWrite(Aic31_PAGE_SELECT_ADDR, Aic31_PAGE_0);
/* Reset the Aic31 */
retVal =
(LLD_hsi2cErrorCode_t) (retVal | I2CWrite(Aic31_P0_REG1, (uint8_t) 0x80));
/* Configure the audio serial data interface mode */
tempData = (0U << 6U);
/* configure the slot width */
tempData |= (3U << 4U);
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite(Aic31_SERIAL_INTERFACEB_ADDR, tempData));
/* Configure sampleRateDiv and dualRate */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG2, (uint8_t) 0,
(uint8_t) 4,
(uint8_t)
sampleRateDiv));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG7, (uint8_t) 5,
(uint8_t) 1,
(uint8_t) dualRate));
/* enable the PLL */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG3, (uint8_t) 7,
(uint8_t) 1,
(uint8_t) 1));
/* select the MCLK as the input for the PLL and CLKDIV(N = 16)*/
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG102,
(uint8_t) 4, (uint8_t) 2,
(uint8_t) 0x00));
/* select the PLL_IN as codec input */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG101,
(uint8_t) 0, (uint8_t) 1,
(uint8_t) 0x00));
/* selec the GPIO to output the divided PLL_IN clock(test purpose)*/
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG98,
(uint8_t) 0x20));
/* Write to PLL programming register A */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG3, (uint8_t) 0,
(uint8_t) 3,
pllPValue));
/* Write to PLL programming register B */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG4, (uint8_t) 2,
(uint8_t) 6,
pllJValue));
/* write the high and low bits of the D value */
retVal =
(LLD_hsi2cErrorCode_t) (retVal | I2CWrite(Aic31_P0_REG5, pllDHighValue));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWrite((uint8_t) Aic31_P0_REG6,
(uint8_t) (pllDLowValue << 2)));
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG11,
(uint8_t) 0, (uint8_t) 4,
pllRValue));
/* Write to codec datapath setup register */
retVal =
(LLD_hsi2cErrorCode_t) (retVal |
I2CWriteBf((uint8_t) Aic31_P0_REG7, (uint8_t) 7,
(uint8_t) 1,
fsRef));
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\n Codec Init failed ", -1);
}
else
{
UARTPuts("\r\n Codec Init successful ", -1);
}
/* Initialize DAC*/
aic31InitDac();
}
static void McASPTXConfigure(void)
{
//step#1
McASPTxReset(SOC_MCASP3_CFG_BASE);
//Step#2 ignored
//step#3
//McASPSetPowerIdleConfig(SOC_MCASP3_CFG_BASE,0x02);
//step#4
/* Set the mask assuming integer format for 32 bit word*/
McASPTxFmtMaskSet(SOC_MCASP3_CFG_BASE, 0xFFFFFFFF);
/* Set I2S format in the transmitter/receiver format units */
McASPTxFmtSet(SOC_MCASP3_CFG_BASE, (MCASP_TX_SYNC_DELAY_0BIT |
MCASP_TX_BITSTREAM_MSB_FIRST |
MCASP_TX_SLOTSIZE_32BITS |
MCASP_TX_ROT_RIGHT_20BITS));
//step$5
McASPTxFrameSyncCfg(SOC_MCASP3_CFG_BASE, I2S_MODE, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_EXT_BEGIN_ON_FALL_EDGE |
MCASP_TX_FS_INTERNAL);
//step#6
/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP3_CFG_BASE, MCASP_TX_CLK_INTERNAL,
((MCASP_ACLKX_CLKXDIV_VALUE & MCASP_ACLKXCTL_CLKXDIV_MASK) >>
MCASP_ACLKXCTL_CLKXDIV_SHIFT),
((MCASP_AHCLKX_HCLKXDIV_VALUE &
MCASP_AHCLKXCTL_HCLKXDIV_MASK) >>
MCASP_AHCLKXCTL_HCLKXDIV_SHIFT));
McASPTxClkPolaritySet(SOC_MCASP3_CFG_BASE, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP3_CFG_BASE, MCASP_TX_CLKCHCK_DIV32, 0x00,
0xFF);
//step#7
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPTxTimeSlotSet(SOC_MCASP3_CFG_BASE, I2S_SLOTS);
//step#8
/*
** Set the serializers
*/
McASPSerializerTxSet(SOC_MCASP3_CFG_BASE, MCASP_XSER_TX_0);
//SOC_MCASP3_CFG_BASE + MCASP_SRCTL(serNum)
//step#9
//this is the default no need to change anything, hence ignore it
//step#10
/*
** Configure the McASP pins
** Output - Frame Sync, Clock, Serializer Rx and Serializer Tx
** (Clocks generated internally)
*/
McASPPinMcASPSet(SOC_MCASP3_CFG_BASE,
(MCASP_PIN_AFSX
| MCASP_PIN_AHCLKX | MCASP_PIN_ACLKX | MCASP_PIN_AMUTE
| MCASP_PIN_AXR(MCASP_XSER_TX_0)
));
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_AFSR);
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_ACLKR);
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_AFSX);
/* Configure high clock as Output */
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_AHCLKX);
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_ACLKX);
/* Both Serializers used to output data out */
McASPPinDirOutputSet(SOC_MCASP3_CFG_BASE, MCASP_PIN_AXR(MCASP_XSER_TX_0));
// I am not sure if we need this or not hence commenting the following section
/* Enable the FIFOs for DMA transfer */
//McASPWriteFifoEnable(SOC_MCASP_3_FIFO_REGS, 1, 1);
}
void McASPTxStatusClr(uint32_t baseAddr, uint32_t statusVal)
{
uint32_t regVal = 0U;
regVal = HW_RD_REG32(baseAddr + MCASP_TXSTAT);
regVal &= ~statusVal;
HW_WR_REG32(baseAddr + MCASP_TXSTAT, regVal);
}
static void TxBufSet(void)
{
int16_t *sineToneDataPtr = NULL;
int32_t *temp;
volatile int32_t buf_val;
uint32_t i = 0;
uint32_t slot_val = 0;
int16_t sent_slot = 0;
int16_t evt_status = 0;
uint32_t serializerStatus=0;
//int8_t xrdy_bit=0;
sineToneDataPtr = _sineWavePattern;
temp = (int32_t *) txBuf0;
*temp = (int32_t) (*sineToneDataPtr);
UARTPuts("\r\nprinting the status at the begining of the txbufset function", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
//McASPTxBufWrite(SOC_MCASP3_CFG_BASE,MCASP_XSER_TX_0, *temp );
McASPTxBufWrite(SOC_MCASP3_CFG_BASE,MCASP_XSER_TX_0, 0x87654321 );
UARTPuts("\r\nprinting the status after writing the txbuf for first time", -1);
buf_val = HW_RD_REG32(SOC_MCASP3_CFG_BASE + MCASP_TXBUF(0));
UARTPuts("\r\ntx buffer value is ", -1);
UARTPutHexNum(buf_val);
serializerStatus = HW_RD_REG32(SOC_MCASP3_CFG_BASE + MCASP_SRCTL(0));
//xrdy_bit = McASPIsSerializerXmtReady(SOC_MCASP3_CFG_BASE,0);
UARTPuts("\r\nserializerStatus ", -1);
UARTPutHexNum(serializerStatus);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
McASPTxEnable(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nprinting the status after enabling the mcasp tx", -1);
serializerStatus = HW_RD_REG32(SOC_MCASP3_CFG_BASE + MCASP_SRCTL(0));
//xrdy_bit = McASPIsSerializerXmtReady(SOC_MCASP3_CFG_BASE,0);
UARTPuts("\r\nserializerStatus ", -1);
UARTPutHexNum(serializerStatus);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
buf_val = HW_RD_REG32(SOC_MCASP3_CFG_BASE + MCASP_TXBUF(0));
UARTPuts("\r\ntx buffer value is ", -1);
UARTPutHexNum(buf_val);
UARTPuts("\r\nMcASP TX Buf set activated ", -1);
slot_val = McASPTxRxTimeSlotGet(SOC_MCASP3_CFG_BASE, (uint8_t) TX);
UARTPuts("\r\nSlot val = ", -1);
UARTPutHexNum(slot_val);
do {
UARTPuts("\r\nSTEP_1 ", -1);
slot_val = McASPTxRxTimeSlotGet(SOC_MCASP3_CFG_BASE, (uint8_t) TX);
UARTPuts("\r\nSlot val = ", -1);
UARTPutHexNum(slot_val);
UARTPuts("\r\nSlot sent = ", -1);
UARTPutHexNum(sent_slot);
UARTPuts("\r\nprinting the status at the begining of the do while loop", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
//HW_WR_REG32(SOC_MCASP3_CFG_BASE + MCASP_TXSTAT, (uint32_t) 0xFFFFU);
//UARTPuts("\r\nTX status = ", -1);
//status = McASPTxStatusGet(SOC_MCASP3_CFG_BASE);
//UARTPutHexNum(status);
while (!(McASPTxStatusGet(SOC_MCASP3_CFG_BASE) & MCASP_TX_STAT_DATAREADY))
{
//UARTPuts("\r\nSTEP_1 hanged ", -1);
//McASPTxEnable(SOC_MCASP3_CFG_BASE);
//McASPTxStatusClr(SOC_MCASP3_CFG_BASE, MCASP_TX_STAT_LASTSLOT);
//do nothing
}
UARTPuts("\r\nSTEP_2 ", -1);
while (!McASPIsSerializerXmtReady(SOC_MCASP3_CFG_BASE, MCASP_XSER_TX_0))
{
UARTPuts("\r\nMcASP TX WAIT TIME ", -1);
}
UARTPuts("\r\nSTEP_3 ", -1);
sent_slot++;
if (McASPTxStatusGet(SOC_MCASP3_CFG_BASE) & MCASP_TXSTAT_XLAST_MASK){
UARTPuts("\r\nSTEP_4 ", -1);
UARTPuts("\r\nprinting the status for step_4 before assering the xlast bit", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
McASPTxStatusSet(SOC_MCASP3_CFG_BASE, MCASP_TX_STAT_LASTSLOT);
UARTPuts("\r\nprinting the status for step_4 after assering the xlast bit", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
temp++;
sineToneDataPtr++;
i++;
*temp = (int32_t) (*sineToneDataPtr);
McASPTxBufWrite(SOC_MCASP3_CFG_BASE,MCASP_XSER_TX_0, *temp );
sent_slot = 0;
if (i == (AUDIO_BUF_SIZE / 4) - 1){
UARTPuts("\r\nprinting the status for step_5", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
UARTPuts("\r\nSTEP_5 ", -1);
UARTPuts("\r\nLoop incremented ", -1);
i = 0;
temp = (int32_t *) txBuf0;
sineToneDataPtr = _sineWavePattern;
*temp = (int32_t) (*sineToneDataPtr);
McASPTxBufWrite(SOC_MCASP3_CFG_BASE,MCASP_XSER_TX_0, *temp );
}
} else {
UARTPuts("\r\nprinting the status for step_6", -1);
McASPTxStatusPrint(SOC_MCASP3_CFG_BASE);
evt_status = McASPTxIntrStatusGet(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nevent status is ", -1);
UARTPutHexNum(evt_status);
UARTPuts("\r\nSTEP_6 ", -1);
temp++;
sineToneDataPtr++;
i++;
*temp = (int32_t) (*sineToneDataPtr);
McASPTxBufWrite(SOC_MCASP3_CFG_BASE,MCASP_XSER_TX_0, *temp );
//sent_slot++;
}
} while (1);
}
void McASPTxSerActivate_polling(uint32_t baseAddr)
{
uint32_t regVal = 0U;
uint32_t slot_val = 0U;
HW_WR_REG32(baseAddr + MCASP_TXSTAT, (uint32_t) 0xFFFFU);
do {
regVal = 0U;
/* Release transmit serializers from reset*/
regVal = HW_RD_REG32(baseAddr + MCASP_GBLCTL);
regVal |= MCASP_GBLCTL_XSRCLR_MASK;
HW_WR_REG32(baseAddr + MCASP_GBLCTL, regVal);
while((HW_RD_REG32(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_XSRCLR_MASK)
!= MCASP_GBLCTL_XSRCLR_MASK)
{
/* Do nothing - Busy wait */
}
//TX value is 1 and identified in mcasp.h file line 69
if (!(McASPTxRxTimeSlotGet(baseAddr, (uint8_t) TX) & 0x1))
{
break;
}
slot_val = McASPTxRxTimeSlotGet(baseAddr, (uint8_t) TX);
UARTPuts("\r\nSlot val = ", -1);
UARTPutHexNum(slot_val);
UARTPuts("\r\nSlot 0 is active ", -1);
} while (!(McASPTxStatusGet(SOC_MCASP3_CFG_BASE) & MCASP_TX_STAT_DATAREADY)) ;
}
/*
** Activates the data transmission/reception
** The DMA parameters shall be ready before calling this function.
*/
static void I2SDataTxActivate_2(void)
{
/* Start the clocks */
McASPTxClkStart(SOC_MCASP3_CFG_BASE, MCASP_TX_CLK_INTERNAL);
UARTPuts("\r\nSTEP 1 : McASP TX activated ", -1);
//we can ignore the following step for now till we use the DMA
/* Enable EDMA for the transfer */
//EDMA3EnableTransfer(SOC_EDMA_TPCC_BASE_VIRT, EDMA3_CHA_MCASP3_TX,
// EDMA3_TRIG_MODE_EVENT);
//disable dma request generation
McASPTxRxDMAEvtCntrlWrite(SOC_MCASP3_CFG_BASE, (uint8_t) TX, 1);
UARTPuts("\r\nSTEP 2 : McASP TX activated ", -1);
/* Activate the serializers */
McASPTxSerActivate_polling(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nSTEP 3 : McASP TX activated ", -1);
/* make sure that the XDATA bit is cleared to zero */
while (!(McASPTxStatusGet(SOC_MCASP3_CFG_BASE) & MCASP_TX_STAT_DATAREADY)) ;
UARTPuts("\r\nSTEP 4 : McASP TX activated ", -1);
/* Activate the state machines */
//McASPTxEnable(SOC_MCASP3_CFG_BASE);
UARTPuts("\r\nSTEP 5 : McASP TX activated ", -1);
}
/*
** Sets up the interrupts for EDMA in AINTC
*/
static void EDMA3IntSetup(void)
{
/*Unlock the Crossbar register */
PlatformUnlockMMR();
#ifdef __ARM_ARCH_7A__
IRQXBARConnect(SOC_IRQ_DMARQ_CROSSBAR_REGISTERS_BASE, CPU_MPUSS, 7,
EDMA_TPCC_IRQ_REGION0);
#elif defined (_TMS320C6X)
IRQXBARConnect(SOC_IRQ_DMARQ_CROSSBAR_REGISTERS_BASE, CPU_DSP1, 7,
EDMA_TPCC_IRQ_REGION2);
#endif
/* Enable The EDMA interrupt */
Intc_Init();
Intc_IntEnable(0);
Intc_IntRegister(EDMA3_CC_XFER_COMPLETION_INT,
(IntrFuncPtr) EDMA3CCComplIsr,
NULL);
Intc_IntPrioritySet(EDMA3_CC_XFER_COMPLETION_INT, 1, 0);
Intc_SystemEnable(EDMA3_CC_XFER_COMPLETION_INT);
}
/*
** Activates the data transmission/reception
** The DMA parameters shall be ready before calling this function.
*/
void sampleConfigScr(unsigned int eventNum, unsigned int chanNum) {
unsigned int scrChanOffset = 0;
unsigned int scrRegOffset = 0;
unsigned int xBarEvtNum = 0;
IntmuxRegsOvly scrEvtMux =
(IntmuxRegsOvly) (EDMA3_EVENT_MUX_REG_BASE_ADDR);
if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&
(chanNum < EDMA3_NUM_TCC))
{
scrRegOffset = chanNum / 2;
scrChanOffset = chanNum - (scrRegOffset * 2);
xBarEvtNum = (eventNum + 1);
switch (scrChanOffset)
{
case 0:
scrEvtMux->TPCC_EVTMUX[scrRegOffset] &=
~(INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
(xBarEvtNum & INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);
break;
case 1:
scrEvtMux->TPCC_EVTMUX[scrRegOffset] &=
~(INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK);
scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=
((xBarEvtNum <<
INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) &
(INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));
break;
default:
break;
}
}
}
/*Configure EDMA Xbar*/
void Configure_Edma_xbar()
{
sampleConfigScr(MCASP3_RX_DMA_XBAR_INST, EDMA3_CHA_MCASP3_TX);
}
/*Pin Mux and Clk config*/
void pinMuxClkConfig(void)
{
/*Unlock the Control registers */
PlatformUnlockMMR();
/* Pad mux configuration for McASP instance 2 */
PlatformMCASP3SetPinMux();
/* Power on McASP instance 2*/
PlatformMCASP3PrcmEnable();
#if (defined (SOC_TDA2XX) || defined (SOC_TDA2PX))
/* Pad mux configuration for I2C instance 2 */
PlatformI2C2SetPinMux();
#elif (defined (SOC_TDA2EX))
/* Pad mux configuration for I2C instance 5 */
PlatformI2C5SetPinMux();
#endif
PlatformUART1SetPinMux();
}
/*Edma Config*/
void edmaConfig(void)
{
#if defined (__ARM_ARCH_7A__)
EDMAsetRegion(EDMA3_CC_REGION_A15);
#elif defined (_TMS320C6X)
EDMAsetRegion(EDMA3_CC_REGION_DSP);
#endif
EDMA3Init(SOC_EDMA_TPCC_BASE_VIRT, EDMA3_CC_QUEUE);
Configure_Edma_xbar();
EDMA3IntSetup();
/* Request EDMA channels */
EDMA3RequestChannel(SOC_EDMA_TPCC_BASE_VIRT, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_CHA_MCASP3_TX, EDMA3_CHA_MCASP3_TX,
EDMA3_CC_QUEUE);
}
static LLD_hsi2cErrorCode_t updateAudioCodecAddr(void)
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
retVal = lld_i2c_probe(i2cHandle, AUDIO_CODEC_SLAVE_ADDR);
if (LLD_HSI2C_SUCCESS != retVal)
{
#ifdef AUDIO_CODEC_SLAVE_ADDR_1
retVal = lld_i2c_probe(i2cHandle, AUDIO_CODEC_SLAVE_ADDR_1);
if (LLD_HSI2C_SUCCESS != retVal)
{
UARTPuts("\r\nProbe to audio codec failed ", -1);
retVal = LLD_HSI2C_FAIL;
}
else
{
/* Use the Alternate Audio Codec Addr */
audioCodecSlaveAddr = AUDIO_CODEC_SLAVE_ADDR_1;
}
#else
UARTPuts("\r\nProbe to audio codec failed ", -1);
retVal = LLD_HSI2C_FAIL;
#endif
}
else
{
/* Use the default Audio Codec Addr */
audioCodecSlaveAddr = AUDIO_CODEC_SLAVE_ADDR;
}
return retVal;
}
/*
** The
** main function. Application starts here.
*/
int main(void)
{
LLD_hsi2cErrorCode_t retVal = LLD_HSI2C_SUCCESS;
/*Pin Mux and Clk config*/
pinMuxClkConfig();
UARTStdioInit();
UARTPuts("\r\nMcASP Sinetone application ", -1);
/*I2C instance 0 init*/
i2c_init(HSI2C_INST_0);
#if (defined (SOC_TDA2XX) || defined (SOC_TDA2PX))
/*I2C instance 1 init*/
i2c_init(HSI2C_INST_1);
#elif (defined (SOC_TDA2EX))
/*I2C instance 1 init*/
i2c_init(HSI2C_INST_4);
#endif
retVal = updateAudioCodecAddr();
if (LLD_HSI2C_SUCCESS != retVal)
{
/* Cannot Probe the audio codec */
while (1) ;
}
/*Clear 6th bit i.e VIN6_SEL_S0 line of IO Expander*/
I2CWrite1(0x00, 0x00);
UARTPuts("\r\nGPIO Expander configured ", -1);
/*Edma Config*/
//edmaConfig();
/*Init Codec and DAC*/
aic31MdCreateChan();
/* Initialize the DMA parameters */
//I2SDMAParamInit();
//UARTPuts("\r\nI2S DMA PAram init done ", -1);
/* Configure the McASP*/
//McASPI2SConfigure();
McASPTXConfigure();
UARTPuts("\r\nMcASP Confgiured ", -1);
/* Activate the audio transmission and reception */
//I2SDataTxActivate();
I2SDataTxActivate_2();
TxBufSet();
/*De-initialize I2C*/
i2c_deinit();
/* Data Transfer happens infinitely even though application ends
* here. Removed while loop as compiler issues warning of non
* returnable main function
*/
return 0;
}
/*
** EDMA transfer completion ISR
*/
static void EDMA3CCComplIsr(void *dummy)
{
/* Check if transmit DMA completed */
if (EDMA3GetIntrStatus(SOC_EDMA_TPCC_BASE_VIRT) & (1 << EDMA3_CHA_MCASP3_TX))
{
/* Clear the interrupt status for the first channel */
EDMA3ClrIntr(SOC_EDMA_TPCC_BASE_VIRT, EDMA3_CHA_MCASP3_TX);
}
}
/***************************** End Of File ***********************************/
While running this sw on the TDA2PXEVM, I can notice the following behavior:
Calling the McASPTxBufWrite api does not change the txbuf, hence when calling the McASPTxEnable api results in an underrun error.
then after continuing and entering the logic of the last slot and clearing the xlast bit in the TXSTAT register, the XDATA bit is set to zero and did not return to 1.
The output of the execution is like the following:
TDA2Px SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed TI EVM PAD Config Completed TDA2Px DDR Configuration DDR Config Completed App Image Download Begins SD Boot - file open completed successfully Trying to boot App Image with header version 1 MPU CPU0 Image Load Completed App Image Download Completed Putting MPU CPU1 in Off mode ***************************************************************** PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles SBL Initial Config Cycles - 118095 (10.7 ms) SOC Init Cycles - 170616 (14.55 ms) DDR Config Clock Cycles - 89617 (7.64 ms) App Image Load Cycles - 893772 (76.26 ms) Slave Core Bootup Cycles - 53856 (4.59 ms) SBL Boot-up Cycles - 1327014 (113.23 ms) Time at which SBL started IPU1_0 - 13390 (408.63 ms) ***************************************************************** Jumping to MPU CPU0 App McASP Sinetone application GPIO Expander configured Codec Init successful DAC Initialization successful McASP Confgiured STEP 1 : McASP TX activated STEP 2 : McASP TX activated Slot val = 0x3 Slot 0 is active STEP 3 : McASP TX activated STEP 4 : McASP TX activated STEP 5 : McASP TX activated printing the status at the begining of the txbufset function -------------TX status ------------ XERR_bit 0x0 XDMAERR_bit 0x0 XSTAFRM_bit 0x0 XDATA_bit 0x1 XLAST_bit 0x0 XTDMSLOT_bit 0x1 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x0 ------------------------------------------ event status is 0x0 printing the status after writing the txbuf for first time tx buffer value is 0x0 serializerStatus 0x11 -------------TX status ------------ XERR_bit 0x0 XDMAERR_bit 0x0 XSTAFRM_bit 0x0 XDATA_bit 0x1 XLAST_bit 0x0 XTDMSLOT_bit 0x1 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x0 ------------------------------------------ event status is 0x0 printing the status after enabling the mcasp tx serializerStatus 0x11 -------------TX status ------------ XERR_bit 0x1 XDMAERR_bit 0x0 XSTAFRM_bit 0x1 XDATA_bit 0x1 XLAST_bit 0x1 XTDMSLOT_bit 0x0 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x1 ------------------------------------------ event status is 0x0 tx buffer value is 0x0 McASP TX Buf set activated Slot val = 0x3 STEP_1 Slot val = 0x3 Slot sent = 0x0 printing the status at the begining of the do while loop -------------TX status ------------ XERR_bit 0x1 XDMAERR_bit 0x0 XSTAFRM_bit 0x1 XDATA_bit 0x1 XLAST_bit 0x1 XTDMSLOT_bit 0x0 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x1 ------------------------------------------ event status is 0x0 STEP_2 STEP_3 STEP_4 printing the status for step_4 before assering the xlast bit -------------TX status ------------ XERR_bit 0x1 XDMAERR_bit 0x0 XSTAFRM_bit 0x1 XDATA_bit 0x1 XLAST_bit 0x1 XTDMSLOT_bit 0x1 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x1 ------------------------------------------ event status is 0x0 printing the status for step_4 after assering the xlast bit -------------TX status ------------ XERR_bit 0x0 XDMAERR_bit 0x0 XSTAFRM_bit 0x1 XDATA_bit 0x0 XLAST_bit 0x1 XTDMSLOT_bit 0x1 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x0 ------------------------------------------ event status is 0x0 STEP_1 Slot val = 0x3 Slot sent = 0x0 printing the status at the begining of the do while loop -------------TX status ------------ XERR_bit 0x0 XDMAERR_bit 0x0 XSTAFRM_bit 0x1 XDATA_bit 0x0 XLAST_bit 0x1 XTDMSLOT_bit 0x1 XCKFAIL_bit 0x0 XSYNCERR_bit 0x0 XUNDRN_bit 0x0 ------------------------------------------ event status is 0x0
So, would you please have a look and let me know if I am missing something?
Thanks in advance for your input and best wishes.
Ahmed