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DRA829J: CPSW9G serdes4_0 clk src register could not write , program stuck at sgmii link state check

Part Number: DRA829J

  Hi:

      when I test cpsw9g    on our board .  I  use minu example to test 9g , 

      we only use  one MAC port 5 (serdes4 lane 0 ),using qsgmii interface  . config as gsgmii main (enabled qsgmii port Marco)

serdes config:

                  /* QSGMII Config */
    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES0;
    serdesLane0EnableParams.baseAddr          = CSL_SERDES_10G0_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;
    serdesLane0EnableParams.numLanes          = 0x2;
    serdesLane0EnableParams.laneMask          = 0x3;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_QSGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = 0;
    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN4;
    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;
    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

clock setting:

    moduleId  = TISCI_DEV_SERDES_10G0;
    clkId     = TISCI_DEV_SERDES_10G0_CORE_REF_CLK;
    clkRateHz = 100000000U;
    EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
    EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);

pdk version: pdk 07_03_00_07     .  PINMUX :I  comment out the Edp pin config 

l launch the code on mcu2_0 core (no other core running except for mcu1_0 sysfirm)

I  try to use FORCEDLINK mode to link phy .But I always find out program stuck at sgmii link state check.

     After debugging ,I find out that when serdes init  ,the CTRLMMR_EDP_PHY0_CLKSEL  register  doesn't change   . After The program run CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(mainCtrlMMRbaseAddr + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL),1,0,0x3);

I read CTRLMMR_EDP_PHY0_CLKSEL value from the CCS registe view ,  It is still  0x02 (suppose to be 0x03 MAIN_PLL2_HSDIV4_CLKOUT )。then the program stuck at sgmii link check .CPSW_SGMII_STATUS_ reg always 0x30.     I have tried AUTONEG_MASTER+AUTONET_SLAVE and config  

phy  (phy STATE IS LINKED UP ),too. but It still stuck at cpsw link state check.   (auto neg complete check). It seem the cpsw0 doesnt working。

   what  may can cause this problem? Is the clock src setting cause this , how to fix it?

Thanks and regards,

  • Hi,

    Sorry for the delay. I will check internally and get back to you by 24th Sep

    Regards

    Vineet

  • The information may be  out-of date.

            Let me first show your our progress first.  .it will help you understand our problem.

    below is  the cpsw9g usage:

        Cpsw 9g(MAC2,sgmii) -> RTL9010aa -> 1000baset1 -> PC

        Cpsw 9g(MAC5,sgmii) -> RTL9010aa -> 1000baset1 -> PC

        PHY have been verified linkde up by read bmsr reg .

      We  test in CCS stuido .  only run main2_0 core ,load with cpsw9g code.

      We have tested cpws9g code on  mac2,mac5.  And  We have managed to make MAC2 (with sgmiiwork.

    Bus mac 5 (with sgmii is still not working .    not linked up 

    the serdes config we are now using  is  like below

        /* SGMII Config */

        serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES0;

        serdesLane0EnableParams.baseAddr          = CSL_SERDES_10G0_BASE;

        serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;

        serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;

        serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;

        serdesLane0EnableParams.numLanes          = 0x2;

        serdesLane0EnableParams.laneMask          = 0x3;

        serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;

        serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;

        serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;

        serdesLane0EnableParams.phyInstanceNum    = 0;

        serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

        serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;

        serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

        serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;

       serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

        CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

        /* Select the IP type, IP instance num, Serdes Lane Number */

        CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,

                           serdesLane0EnableParams.phyType,

                           serdesLane0EnableParams.phyInstanceNum,

                           serdesLane0EnableParams.serdesInstance,

                           0);

     

     

    But issue remain still for MAC5, the  sgmii5  status  seem not link up.    auto neg complete  bit never set

     

    Can you tell us what else  code need be add to make mac5 port work, like add some  additional clk setting or module enable FOR MAC5  ( interface config as sgmii  )?

  • Let me  post where I have changed the pdk  code about  sgmii/serdes config:

    1. main_tirtos.c

        gEnetNimuAppCfg.enetType = ENET_CPSW_9G;

        gEnetNimuAppCfg.instId   = 0U;

        gEnetNimuAppCfg.macPort  = ENET_MAC_PORT_5;

        gEnetNimuAppCfg.boardId  = ENETBOARD_SGMII_ID;

        gEnetNimuAppCfg.mii.layerType    = ENET_MAC_LAYER_GMII;

        gEnetNimuAppCfg.mii.sublayerType = ENET_MAC_SUBLAYER_SERIAL;

    1. enet_board_J7xevm.c

    static const EnetBoard_PortCfg gEnetSgmiiBoard_j721eEthPort[] =

    {

        {

            .enetType = ENET_CPSW_9G,

            .instId   = 0U,

            .macPort  = ENET_MAC_PORT_5,

            .mii      = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },

            .phyCfg   =

            {

                .phyAddr         = 1U,

                .isStrapped      = false,

                .skipExtendedCfg = false,

                .extendedCfg     = NULL,

                .extendedCfgSize = 0U,

            },

            .flags    = (ENET_BOARD_J7XEVM_QPENET_INIT |

                         ENET_BOARD_J7XEVM_SERDES_SIERRA0_CLKS |

                         ENET_BOARD_J7XEVM_SERDES_SIERRA1_CLKS |

                         ENET_BOARD_J7XEVM_SERDES_TORRENT_CLKS),

        },

    };

    1. enet_appboardutils_j721e_evm.c

            case ENET_CPSW_9G:

                if ( ENET_MAC_PORT_1 == portNum ||

                     ENET_MAC_PORT_3 == portNum ||

                     ENET_MAC_PORT_4 == portNum ||

                     ENET_MAC_PORT_8 == portNum )

                {

                    EnetBoard_setPhyConfigRgmii(enetType,

                                                        portNum,

                                                        macCfg,

                                                        interface,

                                                        phyCfg);

                }

                else if ( ENET_MAC_PORT_5 == portNum)

                {

                    EnetBoard_setPhyConfigSgmii(portNum,                                                   

                                                         macCfg,

                                                         interface,

                                                         phyCfg);

                }           

                else

                {

                    EnetBoard_setPhyConfigQsgmii(enetType,

                                                         portNum,

                                                         macCfg,

                                                         interface,

                                                         phyCfg);

                }

                break;

     

    Also I have change Phy address too.

    1. board_serdes_cfg.c

        /* SGMII Config */

        serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES0;

        serdesLane0EnableParams.baseAddr          = CSL_SERDES_10G0_BASE;

        serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;

        serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;

        serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;

        serdesLane0EnableParams.numLanes          = 0x2;

        serdesLane0EnableParams.laneMask          = 0x3;

        serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;

        serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;

        serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;

        serdesLane0EnableParams.phyInstanceNum    = 0;

        serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

        serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;

        serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

        serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;

    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

        CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

        /* Select the IP type, IP instance num, Serdes Lane Number */

        CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,

                          serdesLane0EnableParams.phyType,

                           serdesLane0EnableParams.phyInstanceNum,

                           serdesLane0EnableParams.serdesInstance,

                           0); //serdes4_0

            5. PHY related

      Since  phy  is already link up ,I dont post  the code

    1. Hardware related

      The pdk code is based on evm board ,I delete the useless code like detect board I2C expander.

       AND change pinmux

           7. board_ethernet_config.c

    Board_STATUS Board_ethConfigCpsw9g(void)
    {
    Board_STATUS status = BOARD_SOK;
    uint8_t portNum;

    /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
    RGMII Ports - 1,3,4,8. QSGMII ports - 2 (main),5,6,7 (sub)*/

    /* Configures the CPSW9G RGMII ports */
    for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
    {
    if ( 0U == portNum ||
    2U == portNum ||
    3U == portNum ||
    7U == portNum )
    {
    status = Board_cpsw9gEthConfig(portNum, RGMII);
    }
    else
    {
    if (1U == portNum)
    {
    status = Board_cpsw9gEthConfig(portNum, QSGMII);
    }
    else if (4U == portNum)
    {
    status = Board_cpsw9gEthConfig(portNum, SGMII);
    }
    else
    {
    status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
    }
    }

    if(status != BOARD_SOK)
    {
    return BOARD_FAIL;
    }
    }

    return BOARD_SOK;
    }

     

     

    There may be one question need to be confirmed from  you side first.

    1. Can  cpsw9g MAC5 config as  sgmii mode  ,   connect PHY like RTL9010aa ?
  • Hi, Vineet,

    Do you find anything wrong in Guanjie's modification?

    Thanks.

  • To clarify what is our current question and  situation . I  start a new post 

     https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1043305/dra829v-cpsw9g-mac5-config-as-sgmii-interface-can-not-work

    if you want infomation ,you can refer to this new post.

  • HI , we have encouter a issue when we using cpsw9g

    below is  our cpsw9g   hardware block diag:

    We have tested cpws9g code on port1 ,port2,port5 .  And  We have managed to make port 1,2 (as sgmii interfacework.

    Bus mac 5 (as sgmii interface  does not work.    the   cpsw0_sgmii5  status  reg show it not linked up / auto-neg never completed

    then code end in while loop wait for   sgmii  status reg  set.

    PHY  rtl9010aa  have verfied link up  for all the port.   

    Our code  is based on  RTOS -PDK 8.0  ethfw  code: app_remoteswitch_server  . 

    Below  is code we have changed FOR  test mac5:

    1. main_tirtos.c   

    #if defined(ENABLE_QSGMII_PORTS) //kept it disabled for 6.2
        // {
        //      .portNum    = ENET_MAC_PORT_2, /* QSGMII main */
        //      .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
        {
            .portNum    = ENET_MAC_PORT_5, /* QSGMII sub */
            .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        },
        // {
        //     .portNum    = ENET_MAC_PORT_6, /* QSGMII sub */
        //     .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
        // {
        //     .portNum    = ENET_MAC_PORT_7, /* QSGMII sub */
        //     .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
    #endif
    
    
        /* MAC port used for PTP */
    #if defined(SOC_J721E)
        macPort = ENET_MAC_PORT_5;

    enable only mac5 

    1. enet_board_J7xevm.c

    static const EnetBoard_PortCfg gEnetSgmiiBoard_j721eEthPort[] =
    {
        {
            .enetType = ENET_CPSW_9G,
            .instId   = 0U,
            .macPort  = ENET_MAC_PORT_5,
            .mii      = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
            .phyCfg   =
            {
                .phyAddr         = 1U,
                .isStrapped      = false,
                .skipExtendedCfg = false,
                .extendedCfg     = NULL,
                .extendedCfgSize = 0U,
            },
            .flags    = (ENET_BOARD_J7XEVM_QPENET_INIT |
                         ENET_BOARD_J7XEVM_SERDES_SIERRA0_CLKS |
                         ENET_BOARD_J7XEVM_SERDES_SIERRA1_CLKS |
                         ENET_BOARD_J7XEVM_SERDES_TORRENT_CLKS),
        },
    };

    1. enet_appboardutils_j721e_evm.c

     case ENET_CPSW_9G:
                if ( ENET_MAC_PORT_1 == portNum ||
                     ENET_MAC_PORT_3 == portNum ||
                     ENET_MAC_PORT_4 == portNum ||
                     ENET_MAC_PORT_8 == portNum )
                {
                    EnetBoard_setPhyConfigRgmii(enetType,
                                                        portNum,
                                                        macCfg,
                                                        interface,
                                                        phyCfg);
                }
                else if ( ENET_MAC_PORT_5 == portNum||
                          ENET_MAC_PORT_2 == portNum )
                {
                    EnetBoard_setPhyConfigSgmii(portNum,                                                    
                                                         macCfg,
                                                         interface,
                                                         phyCfg);
                }            
                else
                {
                    EnetBoard_setPhyConfigQsgmii(enetType,
                                                         portNum,
                                                         macCfg,
                                                         interface,
                                                         phyCfg);
                }
                break;

    also I change PHY address according to our hardware.

    4.board_serdes_cfg.c

     /* SGMII Config */
    
        serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES0;
    
        serdesLane0EnableParams.baseAddr          = CSL_SERDES_10G0_BASE;
    
        serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    
        serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    
        serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    
        serdesLane0EnableParams.numLanes          = 0x2;
    
        serdesLane0EnableParams.laneMask          = 0x3;
    
        serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    
        serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    
        serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    
        serdesLane0EnableParams.phyInstanceNum    = 0;
    
        serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;
    
        serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    
        serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;
    
        serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;
    
        CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
    
        /* Select the IP type, IP instance num, Serdes Lane Number */
    
        CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
    
                          serdesLane0EnableParams.phyType,
    
                           serdesLane0EnableParams.phyInstanceNum,
    
                           serdesLane0EnableParams.serdesInstance,
    
                           0); //serdes4_0

    5. app_ehtfw.C

    #if defined(ENABLE_QSGMII_PORTS) //kept it disabled for 6.2
        // {
        //     .portNum    = ENET_MAC_PORT_2, /* QSGMII main */
        //     .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
        {
            .portNum    = ENET_MAC_PORT_5, /* QSGMII sub */
            .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        },
        // {
        //     .portNum    = ENET_MAC_PORT_6, /* QSGMII sub */
        //     .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
        // {
        //     .portNum    = ENET_MAC_PORT_7, /* QSGMII sub */
        //     .vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
        // },
    #endif

    6.board_ethernet_config.c

    Board_STATUS Board_ethConfigCpsw9g(void)
    
    {
    
        Board_STATUS status = BOARD_SOK;
    
        uint8_t portNum;
    
    
    
        /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
    
           RGMII Ports - 1,3,4,8. QSGMII ports - 2 (main),5,6,7 (sub)*/
    
    
    
        /* Configures the CPSW9G RGMII ports */
    
        for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
    
        {
    
            if ( 2U == portNum ||
    
                 3U == portNum ||
    
                 7U == portNum )
    
            {
    
                status = Board_cpsw9gEthConfig(portNum, RGMII);
    
            }
    
            else
    
            {
    
                if (0U == portNum ||
    
                    1U == portNum )
    
                {
    
                    status = Board_cpsw9gEthConfig(portNum, SGMII);
    
                }
    
                else  if (4U == portNum ||
    
                          5U == portNum )
    
                {
    
                    status = Board_cpsw9gEthConfig(portNum, SGMII);
    
                }
    
                else
    
                {
    
                    status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
    
                }
    
            }
    
    
    
            if(status != BOARD_SOK)
    
            {
    
                return BOARD_FAIL;
    
            }
    
        }
    
    
    
        return BOARD_SOK;
    
    }

    7.pHY related:

    Since  phy  is already link up ,I dont post  the code

    8 .Hardware related

      The pdk code is based on evm board ,I delete the useless code like detect board I2C expander.

    below is the CPSW9G sgmii5 reg :

    other related reg dump :

    0216.mac5.txt
    521177 13
    R CTRL_MMR0_CTRLMMR_PID 0x0000000B 0x61800210
    R CTRL_MMR0_CTRLMMR_MMR_CFG1 0x0000000B 0x8000009F
    R CTRL_MMR0_CTRLMMR_MAIN_DEVSTAT 0x0000000B 0x00000047
    R CTRL_MMR0_CTRLMMR_MAIN_BOOTCFG 0x0000000B 0x00000047
    R CTRL_MMR0_CTRLMMR_MAIN_FEATURE_STAT0 0x0000000B 0x00070000
    R CTRL_MMR0_CTRLMMR_MAIN_FEATURE_STAT1 0x0000000B 0x00018FFF
    R CTRL_MMR0_CTRLMMR_IPC_SET6 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET7 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET8 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET9 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET16 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET17 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET18 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET19 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET20 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET21 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET22 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_SET23 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR6 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR7 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR8 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR9 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR16 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR17 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR18 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR19 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR20 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR21 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR22 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_IPC_CLR23 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCI_DEVICE_ID 0x0000000B 0xB00D104C
    R CTRL_MMR0_CTRLMMR_USB_DEVICE_ID 0x0000000B 0x61630451
    R CTRL_MMR0_CTRLMMR_LOCK0_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK0_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_INTR_RAW_STAT 0x0000000B 0x00000004
    R CTRL_MMR0_CTRLMMR_INTR_STAT_CLR 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_INTR_EN_SET 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_INTR_EN_CLR 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EOI 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_FAULT_ADDR 0x0000000B 0x00008090
    R CTRL_MMR0_CTRLMMR_FAULT_TYPE 0x0000000B 0x00000010
    R CTRL_MMR0_CTRLMMR_FAULT_ATTR 0x0000000B 0x000209D4
    R CTRL_MMR0_CTRLMMR_FAULT_CLR 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_USB0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_USB1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ENET1_CTRL 0x0000000B 0x00000012
    R CTRL_MMR0_CTRLMMR_ENET2_CTRL 0x0000000B 0x00000004
    R CTRL_MMR0_CTRLMMR_ENET3_CTRL 0x0000000B 0x00000012
    R CTRL_MMR0_CTRLMMR_ENET4_CTRL 0x0000000B 0x00000012
    R CTRL_MMR0_CTRLMMR_ENET5_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_ENET6_CTRL 0x0000000B 0x00000006
    R CTRL_MMR0_CTRLMMR_ENET7_CTRL 0x0000000B 0x00000006
    R CTRL_MMR0_CTRLMMR_ENET8_CTRL 0x0000000B 0x00000012
    R CTRL_MMR0_CTRLMMR_PCIE0_CTRL 0x0000000B 0x00000103
    R CTRL_MMR0_CTRLMMR_PCIE1_CTRL 0x0000000B 0x00000103
    R CTRL_MMR0_CTRLMMR_PCIE2_CTRL 0x0000000B 0x00000103
    R CTRL_MMR0_CTRLMMR_PCIE3_CTRL 0x0000000B 0x00000103
    R CTRL_MMR0_CTRLMMR_SERDES0_LN0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES0_LN1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES1_LN0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES1_LN1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES2_LN0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES2_LN1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES3_LN0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES3_LN1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES4_LN0_CTRL 0x0000000B 0x00000002
    R CTRL_MMR0_CTRLMMR_SERDES4_LN1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES4_LN2_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES4_LN3_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES2_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES3_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES4_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG0_CTRL0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG0_CTRL1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG1_CTRL0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG1_CTRL1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM2_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM3_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM4_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EPWM5_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SOCA_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SOCB_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EQEP_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SDIO1_CTRL 0x0000000B 0x00000010
    R CTRL_MMR0_CTRLMMR_SDIO2_CTRL 0x0000000B 0x00000011
    R CTRL_MMR0_CTRLMMR_MLB_SIG_IO_CTRL 0x0000000B 0x02010B05
    R CTRL_MMR0_CTRLMMR_MLB_DAT_IO_CTRL 0x0000000B 0x02010B05
    R CTRL_MMR0_CTRLMMR_MLB_CLK_IO_CTRL 0x0000000B 0x00010B05
    R CTRL_MMR0_CTRLMMR_MLB_GPIO_CTRL 0x0000000B 0x00000001
    R CTRL_MMR0_CTRLMMR_TIMER0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER2_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER3_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER4_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER5_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER6_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER7_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER8_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER9_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER10_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER11_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER12_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER13_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER14_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER15_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER16_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER17_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER18_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER19_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO2_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO3_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO4_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO5_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO6_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMERIO7_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_I3C0_CTRL0 0x0000000B 0x01020000
    R CTRL_MMR0_CTRLMMR_I3C0_CTRL1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_I3C1_CTRL0 0x0000000B 0x01020000
    R CTRL_MMR0_CTRLMMR_I3C1_CTRL1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_I2C0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_I2C1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DPHY_TX0_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_CSI_RX_LOOPBACK 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_GPU_GP_IN_REQ 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_GPU_GP_IN_ACK 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_GPU_GP_OUT_REQ 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_GPU_GP_OUT_ACK 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_LOCK1_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK1_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_OBSCLK0_CTRL 0x0000000B 0x0000001F
    R CTRL_MMR0_CTRLMMR_OBSCLK1_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_CLKOUT_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_GTC_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EFUSE_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ICSSG1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE_REFCLK0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE_REFCLK1_CLKSEL 0x0000000B 0x00000001
    R CTRL_MMR0_CTRLMMR_PCIE_REFCLK2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE_REFCLK3_CLKSEL 0x0000000B 0x00000001
    R CTRL_MMR0_CTRLMMR_PCIE0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PCIE3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_CPSW_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_NAVSS_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EMMC0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EMMC1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EMMC2_CLKSEL 0x0000000B 0x00000002
    R CTRL_MMR0_CTRLMMR_UFS0_CLKSEL 0x0000000B 0x00000002
    R CTRL_MMR0_CTRLMMR_GPMC_CLKSEL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USB0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_USB1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER4_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER5_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER6_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER7_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER8_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER9_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER10_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER11_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER12_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER13_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER14_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER15_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER16_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER17_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER18_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_TIMER19_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI5_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI6_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SPI7_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_USART0_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART1_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART2_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART3_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART4_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART5_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART6_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART7_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART8_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_USART9_CLK_CTRL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_MCASP0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP4_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP5_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP6_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP7_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP8_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP9_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP10_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP11_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP0_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP1_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP2_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP3_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP4_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP5_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP6_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP7_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP8_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP9_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP10_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCASP11_AHCLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_RXSYNC0_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_RXSYNC1_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_RXSYNC2_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_RXSYNC3_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_TXSYNC0_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_TXSYNC1_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_TXSYNC2_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ASRC_TXSYNC3_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_BWS0_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_BWS1_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_BWS2_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_BWS3_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_AWS0_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_AWS1_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_AWS2_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_AWS3_SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_ATL_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_AUDIO_REFCLK0_CTRL 0x0000000B 0x0000001F
    R CTRL_MMR0_CTRLMMR_AUDIO_REFCLK1_CTRL 0x0000000B 0x0000001F
    R CTRL_MMR0_CTRLMMR_AUDIO_REFCLK2_CTRL 0x0000000B 0x0000001F
    R CTRL_MMR0_CTRLMMR_AUDIO_REFCLK3_CTRL 0x0000000B 0x0000001F
    R CTRL_MMR0_CTRLMMR_DPI0_CLK_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DPI1_CLK_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DPHY0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSS_DISPC0_CLKSEL1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSS_DISPC0_CLKSEL2 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSS_DISPC0_CLKSEL3 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_EDP_PHY0_CLKSEL 0x0000000B 0x00000003
    R CTRL_MMR0_CTRLMMR_EDP0_CLK_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD15_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD16_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD24_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD25_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD28_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD29_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD30_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_WWD31_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES0_CLKSEL 0x0000000B 0x00000002
    R CTRL_MMR0_CTRLMMR_SERDES0_CLK1SEL 0x0000000B 0x00000002
    R CTRL_MMR0_CTRLMMR_SERDES1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES1_CLK1SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES2_CLK1SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_SERDES3_CLK1SEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN0_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN1_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN2_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN3_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN4_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN5_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN6_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN7_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN8_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN9_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN10_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN11_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN12_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCAN13_CLKSEL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_LOCK2_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK2_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_CTRL 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_PATCOUNT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_SEED0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_SEED1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_SPARE0 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_SPARE1 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_MISR 0x0000000B 0x61400000
    R CTRL_MMR0_CTRLMMR_MCU0_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MCU1_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DMPAC_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_VPAC_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DSP0_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_MPU0_LBIST_SIG 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_FUSE_CRC_STAT 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_LOCK3_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK3_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_CHNG_DDR4_FSP_REQ 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_CHNG_DDR4_FSP_ACK 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DDR4_FSP_CLKCHNG_REQ 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_DDR4_FSP_CLKCHNG_ACK 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_LOCK5_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK5_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_ACSPCIE0_CTRL 0x0000000B 0x01000003
    R CTRL_MMR0_CTRLMMR_ACSPCIE1_CTRL 0x0000000B 0x01000003
    R CTRL_MMR0_CTRLMMR_LOCK6_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK6_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_PADCONFIG0 0x0000000B 0x00040007
    R CTRL_MMR0_CTRLMMR_PADCONFIG1 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG2 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG3 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG4 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG5 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG6 0x0000000B 0x00010003
    R CTRL_MMR0_CTRLMMR_PADCONFIG7 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG8 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG9 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG10 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG11 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG12 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG13 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG14 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG15 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG16 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG17 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG18 0x0000000B 0x08054000
    R CTRL_MMR0_CTRLMMR_PADCONFIG19 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG20 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG21 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG22 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG23 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG24 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG25 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG26 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG27 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG28 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG29 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG30 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG31 0x0000000B 0x00050002
    R CTRL_MMR0_CTRLMMR_PADCONFIG32 0x0000000B 0x00010002
    R CTRL_MMR0_CTRLMMR_PADCONFIG33 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG34 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG35 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG36 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG37 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG38 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG39 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG40 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG41 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG42 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG43 0x0000000B 0x00050005
    R CTRL_MMR0_CTRLMMR_PADCONFIG44 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG45 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG46 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG47 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG48 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG49 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG50 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG51 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG52 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG53 0x0000000B 0x00060004
    R CTRL_MMR0_CTRLMMR_PADCONFIG54 0x0000000B 0x00060004
    R CTRL_MMR0_CTRLMMR_PADCONFIG55 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG56 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG57 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG58 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG59 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG60 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG61 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG62 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG63 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG64 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG65 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG66 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG67 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG68 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG69 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG70 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG71 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG72 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG73 0x0000000B 0x0005000E
    R CTRL_MMR0_CTRLMMR_PADCONFIG74 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG75 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG76 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG77 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG78 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG79 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG80 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG81 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG82 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG83 0x0000000B 0x00050004
    R CTRL_MMR0_CTRLMMR_PADCONFIG84 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG85 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG86 0x0000000B 0x00050006
    R CTRL_MMR0_CTRLMMR_PADCONFIG87 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG88 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG89 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG90 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG91 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG92 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG93 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG94 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG95 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG96 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG97 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG98 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG99 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG100 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG101 0x0000000B 0x00010001
    R CTRL_MMR0_CTRLMMR_PADCONFIG102 0x0000000B 0x00010001
    R CTRL_MMR0_CTRLMMR_PADCONFIG103 0x0000000B 0x00010001
    R CTRL_MMR0_CTRLMMR_PADCONFIG104 0x0000000B 0x00010001
    R CTRL_MMR0_CTRLMMR_PADCONFIG105 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG106 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG107 0x0000000B 0x0005000C
    R CTRL_MMR0_CTRLMMR_PADCONFIG108 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG109 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG110 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG111 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG112 0x0000000B 0x00010001
    R CTRL_MMR0_CTRLMMR_PADCONFIG113 0x0000000B 0x00010006
    R CTRL_MMR0_CTRLMMR_PADCONFIG114 0x0000000B 0x00060002
    R CTRL_MMR0_CTRLMMR_PADCONFIG115 0x0000000B 0x00060002
    R CTRL_MMR0_CTRLMMR_PADCONFIG116 0x0000000B 0x00060002
    R CTRL_MMR0_CTRLMMR_PADCONFIG117 0x0000000B 0x00050001
    R CTRL_MMR0_CTRLMMR_PADCONFIG118 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG119 0x0000000B 0x00050003
    R CTRL_MMR0_CTRLMMR_PADCONFIG120 0x0000000B 0x00010003
    R CTRL_MMR0_CTRLMMR_PADCONFIG121 0x0000000B 0x00060002
    R CTRL_MMR0_CTRLMMR_PADCONFIG122 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG123 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG124 0x0000000B 0x00050003
    R CTRL_MMR0_CTRLMMR_PADCONFIG125 0x0000000B 0x00010003
    R CTRL_MMR0_CTRLMMR_PADCONFIG126 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG127 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG128 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG129 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG130 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG131 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG132 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG133 0x0000000B 0x00010004
    R CTRL_MMR0_CTRLMMR_PADCONFIG134 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG135 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG136 0x0000000B 0x00040000
    R CTRL_MMR0_CTRLMMR_PADCONFIG137 0x0000000B 0x00040000
    R CTRL_MMR0_CTRLMMR_PADCONFIG138 0x0000000B 0x00040000
    R CTRL_MMR0_CTRLMMR_PADCONFIG139 0x0000000B 0x00040000
    R CTRL_MMR0_CTRLMMR_PADCONFIG140 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG141 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG142 0x0000000B 0x00010002
    R CTRL_MMR0_CTRLMMR_PADCONFIG143 0x0000000B 0x00010002
    R CTRL_MMR0_CTRLMMR_PADCONFIG144 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG145 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG146 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG147 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG148 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG149 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG150 0x0000000B 0x00060000
    R CTRL_MMR0_CTRLMMR_PADCONFIG151 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG152 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG153 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG154 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG155 0x0000000B 0x00050007
    R CTRL_MMR0_CTRLMMR_PADCONFIG156 0x0000000B 0x00060004
    R CTRL_MMR0_CTRLMMR_PADCONFIG157 0x0000000B 0x00060004
    R CTRL_MMR0_CTRLMMR_PADCONFIG158 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG159 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG160 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG161 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG162 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG163 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG164 0x0000000B 0x00010000
    R CTRL_MMR0_CTRLMMR_PADCONFIG165 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG166 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG167 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG168 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG169 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG170 0x0000000B 0x00000000
    R CTRL_MMR0_CTRLMMR_PADCONFIG171 0x0000000B 0x00050000
    R CTRL_MMR0_CTRLMMR_PADCONFIG172 0x0000000B 0x08214000
    R CTRL_MMR0_CTRLMMR_LOCK7_KICK0 0x0000000B 0x68EF3491
    R CTRL_MMR0_CTRLMMR_LOCK7_KICK1 0x0000000B 0xD172BC5A
    R CTRL_MMR0_CTRLMMR_IPC_SET0 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXGOODFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXBROADCASTFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXMULTICASTFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXPAUSEFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXCRCERRORS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXALIGNCODEERRORS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXOVERSIZEDFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXJABBERFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXUNDERSIZEDFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXFRAGMENTS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_OVERRUN_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXOCTETS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXGOODFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXBROADCASTFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXMULTICASTFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXPAUSEFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXDEFERREDFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXCOLLISIONFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXSINGLECOLLFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXMULTCOLLFRAMES_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXEXCESSIVECOLLISIONS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXLATECOLLISIONS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RXIPGERROR_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXCARRIERSENSEERRORS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TXOCTETS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES64_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES65T127_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES128T255_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES256T511_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES512T1023_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_OCTETFRAMES1024TUP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_NETOCTETS_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RX_BOTTOM_OF_FIFO_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_PORTMASK_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_RX_TOP_OF_FIFO_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_RATE_LIMIT_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_VID_INGRESS_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_DA_EQ_SA_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_BLOCK_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_SECURE_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_AUTH_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_UNI_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_UNI_BCNT_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_MLT_K 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_MLT_BCNT_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_BRD_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_UNKN_BRD_BCNT_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_POL_MATCH_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_POL_MATCH_RED_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_POL_MATCH_YELLOW_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_MULT_SA_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_DUAL_VLAN_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_LEN_ERROR_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_IP_NEXT_HDR_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ALE_IPV4_FRAG_DROP_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_RX_ASSEMBLY_ERROR_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_RX_ASSEMBLY_OK_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_RX_SMD_ERROR_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_RX_FRAG_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_TX_HOLD_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_IET_TX_FRAG_REG_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_TX_MEMORY_PROTECT_ERROR_k 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ENET_PN_TX_PRI_REG_k_y 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ENET_PN_TX_PRI_BCNT_REG_k_y 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ENET_PN_TX_PRI_DROP_REG_k_y 0x0000000B 0x00000000
    R CPSW0_NUSS_CPSW_STAT_ENET_PN_TX_PRI_DROP_BCNT_REG_k_y 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_REV 0x0000000B 0x66A0EA00
    R CPSW0_ECC_CPSW_ECC_VECTOR 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_STAT 0x0000000B 0x00000014
    R CPSW0_ECC_CPSW_ECC_RESERVED_SVBUS_y 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_SEC_EOI_REG 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_SEC_STATUS_REG0 0x0000000B 0x00000001
    R CPSW0_ECC_CPSW_ECC_SEC_ENABLE_SET_REG0 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_SEC_ENABLE_CLR_REG0 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_DED_EOI_REG 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_DED_STATUS_REG0 0x0000000B 0x00000001
    R CPSW0_ECC_CPSW_ECC_DED_ENABLE_SET_REG0 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_DED_ENABLE_CLR_REG0 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_AGGR_ENABLE_SET 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_AGGR_ENABLE_CLR 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_AGGR_STATUS_SET 0x0000000B 0x00000000
    R CPSW0_ECC_CPSW_ECC_AGGR_STATUS_CLR 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PID_TYPE 0x0000000B 0x00007364
    R SERDES_10G0_CMN_PID_NUM 0x0000000B 0x08010000
    R SERDES_10G0_CMN_PID_REV 0x0000000B 0x00000120
    R SERDES_10G0_CMN_PID_NODE__CMN_PID_MFG 0x0000000B 0x00160074
    R SERDES_10G0_CMN_PID_FLV1__CMN_PID_FLV0 0x0000000B 0x63006666
    R SERDES_10G0_CMN_PID_LANES__CMN_PID_IOV 0x0000000B 0x02020120
    R SERDES_10G0_CMN_PID_METAL1__CMN_PID_METAL0 0x0000000B 0x00041020
    R SERDES_10G0_CMN_PID_METAL3__CMN_PID_METAL2 0x0000000B 0x00200000
    R SERDES_10G0_CMN_PID_METALD 0x0000000B 0x00000155
    R SERDES_10G0_CMN_SSM_BANDGAP_TMR__CMN_SSM_SM_CTRL 0x0000000B 0x00010003
    R SERDES_10G0_CMN_SSM_BIAS_TMR 0x0000000B 0x00000019
    R SERDES_10G0_CMN_SSM_USER_DEF_CTRL 0x0000000B 0x00010000
    R SERDES_10G0_CMN_PLLSM0_PLLEN_TMR__CMN_PLLSM0_SM_CTRL 0x0000000B 0x00040001
    R SERDES_10G0_CMN_PLLSM0_PLLVREF_TMR__CMN_PLLSM0_PLLPRE_TMR 0x0000000B 0x00010032
    R SERDES_10G0_CMN_PLLSM0_PLLCLKDIS_TMR__CMN_PLLSM0_PLLLOCK_TMR 0x0000000B 0x000100D1
    R SERDES_10G0_CMN_PLLSM0_USER_DEF_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLLSM1_PLLEN_TMR__CMN_PLLSM1_SM_CTRL 0x0000000B 0x00040001
    R SERDES_10G0_CMN_PLLSM1_PLLVREF_TMR__CMN_PLLSM1_PLLPRE_TMR 0x0000000B 0x00010032
    R SERDES_10G0_CMN_PLLSM1_PLLCLKDIS_TMR__CMN_PLLSM1_PLLLOCK_TMR 0x0000000B 0x000100D1
    R SERDES_10G0_CMN_PLLSM1_USER_DEF_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_CDIAG_CDB_PWRI_OVRD__CMN_CDIAG_PWRI_TMR 0x0000000B 0x01240101
    R SERDES_10G0_CMN_CDIAG_PLLC_PWRI_OVRD__CMN_CDIAG_CDB_PWRI_STAT 0x0000000B 0x0124003B
    R SERDES_10G0_CMN_CDIAG_CCAL_PWRI_OVRD__CMN_CDIAG_PLLC_PWRI_STAT 0x0000000B 0x0424003B
    R SERDES_10G0_CMN_CDIAG_XCVRC_PWRI_OVRD__CMN_CDIAG_CCAL_PWRI_STAT 0x0000000B 0x012400A6
    R SERDES_10G0_CMN_CDIAG_DIAG_PWRI_OVRD__CMN_CDIAG_XCVRC_PWRI_STAT 0x0000000B 0x0424003B
    R SERDES_10G0_CMN_CDIAG_PRATECLK_CTRL__CMN_CDIAG_DIAG_PWRI_STAT 0x0000000B 0x000000A4
    R SERDES_10G0_CMN_CDIAG_REFCLK_TEST__CMN_CDIAG_REFCLK_OVRD 0x0000000B 0x00000108
    R SERDES_10G0_CMN_CDIAG_SDOSC_CTRL__CMN_CDIAG_PSMCLK_CTRL 0x0000000B 0x00000005
    R SERDES_10G0_CMN_CDIAG_REFCLK_DRV0_CTRL 0x0000000B 0x00000242
    R SERDES_10G0_CMN_CDIAG_RST_DIAG__CMN_CDIAG_CDB_DIAG 0x0000000B 0x00030000
    R SERDES_10G0_CMN_CDIAG_DCYA 0x0000000B 0x00000000
    R SERDES_10G0_CMN_BGCAL_OVRD__CMN_BGCAL_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_BGCAL_TUNE__CMN_BGCAL_START 0x0000000B 0x00000000
    R SERDES_10G0_CMN_BGCAL_ITER_TMR__CMN_BGCAL_INIT_TMR 0x0000000B 0x007D007D
    R SERDES_10G0_CMN_IBCAL_OVRD__CMN_IBCAL_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_IBCAL_TUNE__CMN_IBCAL_START 0x0000000B 0x0000001F
    R SERDES_10G0_CMN_IBCAL_ITER_TMR__CMN_IBCAL_INIT_TMR 0x0000000B 0x00070019
    R SERDES_10G0_CMN_PLL0_VCOCAL_START__CMN_PLL0_VCOCAL_CTRL 0x0000000B 0x2028002D
    R SERDES_10G0_CMN_PLL0_VCOCAL_OVRD__CMN_PLL0_VCOCAL_TCTRL 0x0000000B 0x00000003
    R SERDES_10G0_CMN_PLL0_VCOCAL_ITER_TMR__CMN_PLL0_VCOCAL_INIT_TMR 0x0000000B 0x001003E8
    R SERDES_10G0_CMN_PLL0_VCOCAL_REFTIM_START 0x0000000B 0x00000C5F
    R SERDES_10G0_CMN_PLL0_VCOCAL_PLLCNT_START 0x0000000B 0x00000C5F
    R SERDES_10G0_CMN_PLL0_FRACDIVL_M0__CMN_PLL0_INTDIV_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL0_HIGH_THR_M0__CMN_PLL0_FRACDIVH_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL0_DSM_FBH_OVRD_M0__CMN_PLL0_DSM_DIAG_M0 0x0000000B 0x001E4004
    R SERDES_10G0_CMN_PLL0_DSM_FBL_OVRD_M0 0x0000000B 0x0000000C
    R SERDES_10G0_CMN_PLL0_SS_CTRL2_M0__CMN_PLL0_SS_CTRL1_M0 0x0000000B 0x00000002
    R SERDES_10G0_CMN_PLL0_SS_CTRL4_M0__CMN_PLL0_SS_CTRL3_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL0_LOCK_REFCNT_IDLE__CMN_PLL0_LOCK_REFCNT_START 0x0000000B 0x000400C8
    R SERDES_10G0_CMN_PLL0_LOCK_PLLCNT_THR__CMN_PLL0_LOCK_PLLCNT_START 0x0000000B 0x000300C8
    R SERDES_10G0_CMN_PLL0_FRACDIVL_M1__CMN_PLL0_INTDIV_M1 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL0_HIGH_THR_M1__CMN_PLL0_FRACDIVH_M1 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL0_DSM_FBH_OVRD_M1__CMN_PLL0_DSM_DIAG_M1 0x0000000B 0x00104004
    R SERDES_10G0_CMN_PLL0_DSM_FBL_OVRD_M1 0x0000000B 0x00000010
    R SERDES_10G0_CMN_PLL0_SS_CTRL2_M1__CMN_PLL0_SS_CTRL1_M1 0x0000000B 0x00000002
    R SERDES_10G0_CMN_PLL0_SS_CTRL4_M1__CMN_PLL0_SS_CTRL3_M1 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL1_VCOCAL_START__CMN_PLL1_VCOCAL_CTRL 0x0000000B 0x20280092
    R SERDES_10G0_CMN_PLL1_VCOCAL_OVRD__CMN_PLL1_VCOCAL_TCTRL 0x0000000B 0x00000003
    R SERDES_10G0_CMN_PLL1_VCOCAL_ITER_TMR__CMN_PLL1_VCOCAL_INIT_TMR 0x0000000B 0x001003E8
    R SERDES_10G0_CMN_PLL1_VCOCAL_REFTIM_START 0x0000000B 0x00000C5F
    R SERDES_10G0_CMN_PLL1_VCOCAL_PLLCNT_START 0x0000000B 0x00000C5F
    R SERDES_10G0_CMN_PLL1_FRACDIVL_M0__CMN_PLL1_INTDIV_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL1_HIGH_THR_M0__CMN_PLL1_FRACDIVH_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL1_DSM_FBH_OVRD_M0__CMN_PLL1_DSM_DIAG_M0 0x0000000B 0x00104004
    R SERDES_10G0_CMN_PLL1_DSM_FBL_OVRD_M0 0x0000000B 0x00000010
    R SERDES_10G0_CMN_PLL1_SS_CTRL2_M0__CMN_PLL1_SS_CTRL1_M0 0x0000000B 0x00000002
    R SERDES_10G0_CMN_PLL1_SS_CTRL4_M0__CMN_PLL1_SS_CTRL3_M0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PLL1_LOCK_REFCNT_IDLE__CMN_PLL1_LOCK_REFCNT_START 0x0000000B 0x000400C8
    R SERDES_10G0_CMN_PLL1_LOCK_PLLCNT_THR__CMN_PLL1_LOCK_PLLCNT_START 0x0000000B 0x000300C8
    R SERDES_10G0_CMN_TXPUCAL_OVRD__CMN_TXPUCAL_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_TXPUCAL_TUNE__CMN_TXPUCAL_START 0x0000000B 0x0008002D
    R SERDES_10G0_CMN_TXPUCAL_ITER_TMR__CMN_TXPUCAL_INIT_TMR 0x0000000B 0x0006001E
    R SERDES_10G0_CMN_TXPDCAL_OVRD__CMN_TXPDCAL_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_TXPDCAL_TUNE__CMN_TXPDCAL_START 0x0000000B 0x0008802D
    R SERDES_10G0_CMN_TXPDCAL_ITER_TMR__CMN_TXPDCAL_INIT_TMR 0x0000000B 0x0006001E
    R SERDES_10G0_CMN_RXCAL_OVRD__CMN_RXCAL_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_RXCAL_TUNE__CMN_RXCAL_START 0x0000000B 0x00000008
    R SERDES_10G0_CMN_RXCAL_ITER_TMR__CMN_RXCAL_INIT_TMR 0x0000000B 0x000602EE
    R SERDES_10G0_CMN_SD_CAL_START__CMN_SD_CAL_CTRL 0x0000000B 0x101E0000
    R SERDES_10G0_CMN_SD_CAL_OVRD__CMN_SD_CAL_TCTRL 0x0000000B 0x00000001
    R SERDES_10G0_CMN_SD_CAL_ITER_TMR__CMN_SD_CAL_INIT_TMR 0x0000000B 0x00020006
    R SERDES_10G0_CMN_SD_CAL_REFTIM_START 0x0000000B 0x0000000E
    R SERDES_10G0_CMN_SD_CAL_PLLCNT_START 0x0000000B 0x0000012B
    R SERDES_10G0_CMN_CMSMT_TEST_CLK_SEL__CMN_CMSMT_CLK_FREQ_MSMT_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_CMN_CMSMT_TEST_CLK_CNT_VALUE__CMN_CMSMT_REF_CLK_TMR_VALUE 0x0000000B 0x00000000
    R SERDES_10G0_CMN_PDIAG_PLL0_CLK_SEL_M0__CMN_PDIAG_PLL0_CTRL_M0 0x0000000B 0x06011012
    R SERDES_10G0_CMN_PDIAG_PLL0_ITRIM_M0__CMN_PDIAG_PLL0_OVRD_M0 0x0000000B 0x000F0000
    R SERDES_10G0_CMN_PDIAG_PLL0_CP_IADJ_M0__CMN_PDIAG_PLL0_CP_PADJ_M0 0x0000000B 0x08080028
    R SERDES_10G0_CMN_PDIAG_PLL0_CP_TUNE_M0__CMN_PDIAG_PLL0_FILT_PADJ_M0 0x0000000B 0x00010000
    R SERDES_10G0_CMN_PDIAG_PLL0_CLK_SEL_M1__CMN_PDIAG_PLL0_CTRL_M1 0x0000000B 0x04001012
    R SERDES_10G0_CMN_PDIAG_PLL0_ITRIM_M1__CMN_PDIAG_PLL0_OVRD_M1 0x0000000B 0x000F0000
    R SERDES_10G0_CMN_PDIAG_PLL0_CP_IADJ_M1__CMN_PDIAG_PLL0_CP_PADJ_M1 0x0000000B 0x08080128
    R SERDES_10G0_CMN_PDIAG_PLL0_CP_TUNE_M1__CMN_PDIAG_PLL0_FILT_PADJ_M1 0x0000000B 0x00010000
    R SERDES_10G0_CMN_PDIAG_PLL1_CLK_SEL_M0__CMN_PDIAG_PLL1_CTRL_M0 0x0000000B 0x04001012
    R SERDES_10G0_CMN_PDIAG_PLL1_ITRIM_M0__CMN_PDIAG_PLL1_OVRD_M0 0x0000000B 0x000F0000
    R SERDES_10G0_CMN_PDIAG_PLL1_CP_IADJ_M0__CMN_PDIAG_PLL1_CP_PADJ_M0 0x0000000B 0x08080128
    R SERDES_10G0_CMN_PDIAG_PLL1_CP_TUNE_M0__CMN_PDIAG_PLL1_FILT_PADJ_M0 0x0000000B 0x00010000
    R SERDES_10G0_CMN_DIAG_BIAS_OVRD1__CMN_DIAG_BANDGAP_OVRD 0x0000000B 0x37000E05
    R SERDES_10G0_CMN_DIAG_VREG_CTRL__CMN_DIAG_BIAS_OVRD2 0x0000000B 0x00000000
    R SERDES_10G0_CMN_DIAG_SH_BANDGAP__CMN_DIAG_PM_CTRL 0x0000000B 0x002A0000
    R SERDES_10G0_CMN_DIAG_SH_SDCLK__CMN_DIAG_SH_RESISTOR 0x0000000B 0x000C3709
    R SERDES_10G0_CMN_DIAG_ATB_CTRL2__CMN_DIAG_ATB_CTRL1 0x0000000B 0x00000000
    R SERDES_10G0_CMN_DIAG_ATB_ADC_CTRL1__CMN_DIAG_ATB_ADC_CTRL0 0x0000000B 0x00000000
    R SERDES_10G0_CMN_DIAG_RST_DIAG__CMN_DIAG_HSRRSM_CTRL 0x0000000B 0x01FF0011
    R SERDES_10G0_CMN_DIAG_ACYA__CMN_DIAG_DCYA 0x0000000B 0x00000000
    R SERDES_10G0_MOD_VER 0x0000000B 0x698A6002
    R SERDES_10G0_SERDES_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_SERDES_TOP_CTRL 0x0000000B 0x18000000
    R SERDES_10G0_SERDES_RST 0x0000000B 0xB1000000
    R SERDES_10G0_SERDES_TYPEC 0x0000000B 0x00000000
    R SERDES_10G0_LANECTL0 0x0000000B 0x70800000
    R SERDES_10G0_LANEDIV0 0x0000000B 0x00010002
    R SERDES_10G0_LANALIGN0 0x0000000B 0x00000000
    R SERDES_10G0_LANESTS0 0x0000000B 0x00000002
    R SERDES_10G0_LANECTL1 0x0000000B 0x70800000
    R SERDES_10G0_LANEDIV1 0x0000000B 0x00010002
    R SERDES_10G0_LANALIGN1 0x0000000B 0x00000005
    R SERDES_10G0_LANESTS1 0x0000000B 0x00000000
    R SERDES_10G0_LANECTL2 0x0000000B 0x00000000
    R SERDES_10G0_LANEDIV2 0x0000000B 0x00000000
    R SERDES_10G0_LANALIGN2 0x0000000B 0x00000000
    R SERDES_10G0_LANESTS2 0x0000000B 0x00000000
    R SERDES_10G0_LANECTL3 0x0000000B 0x00000000
    R SERDES_10G0_LANEDIV3 0x0000000B 0x00000000
    R SERDES_10G0_LANALIGN3 0x0000000B 0x00000000
    R SERDES_10G0_LANESTS3 0x0000000B 0x00000000
    R SERDES_10G0_DTB_MUX_SEL 0x0000000B 0x00000000
    R SERDES_10G0_DIAG_TEST 0x0000000B 0x00000000
    R SERDES_10G0_XCVR_PSM_RCTRL__XCVR_PSM_CTRL_j 0x0000000B 0xBCFC0201
    R SERDES_10G0_XCVR_PSM_A0IN_TMR__XCVR_PSM_CALIN_TMR_j 0x0000000B 0x00960096
    R SERDES_10G0_XCVR_PSM_A1IN_TMR__XCVR_PSM_A0BYP_TMR_j 0x0000000B 0x0010000A
    R SERDES_10G0_XCVR_PSM_A3IN_TMR__XCVR_PSM_A2IN_TMR_j 0x0000000B 0x00100010
    R SERDES_10G0_XCVR_PSM_A5IN_TMR__XCVR_PSM_A4IN_TMR_j 0x0000000B 0x00100010
    R SERDES_10G0_XCVR_PSM_A0OUT_TMR__XCVR_PSM_CALOUT_TMR_j 0x0000000B 0x00010001
    R SERDES_10G0_XCVR_PSM_A2OUT_TMR__XCVR_PSM_A1OUT_TMR_j 0x0000000B 0x00010001
    R SERDES_10G0_XCVR_PSM_A4OUT_TMR__XCVR_PSM_A3OUT_TMR_j 0x0000000B 0x00010001
    R SERDES_10G0_XCVR_PSM_RDY_TMR__XCVR_PSM_A5OUT_TMR_j 0x0000000B 0x00100001
    R SERDES_10G0_XCVR_PSM_ST_0__XCVR_PSM_DIAG_j 0x0000000B 0x00010000
    R SERDES_10G0_XCVR_PSM_ST_1_j 0x0000000B 0x00000200
    R SERDES_10G0_XCVR_PSM_USER_DEF_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_PRE_OVRD__TX_TXCC_CTRL_j 0x0000000B 0x00002A84
    R SERDES_10G0_TX_TXCC_POST_OVRD__TX_TXCC_MAIN_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_MAIN_CVAL__TX_TXCC_PRE_CVAL_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_LF_MULT__TX_TXCC_POST_CVAL_j 0x0000000B 0x002A0000
    R SERDES_10G0_TX_TXCC_CPRE_MULT_01__TX_TXCC_CPRE_MULT_00_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_CPRE_MULT_11__TX_TXCC_CPRE_MULT_10_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_CPOST_MULT_01__TX_TXCC_CPOST_MULT_00_j 0x0000000B 0x00110000
    R SERDES_10G0_TX_TXCC_CPOST_MULT_11__TX_TXCC_CPOST_MULT_10_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_MGNFS_MULT_001__TX_TXCC_MGNFS_MULT_000_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_MGNFS_MULT_011__TX_TXCC_MGNFS_MULT_010_j 0x0000000B 0x000F0007
    R SERDES_10G0_TX_TXCC_MGNFS_MULT_101__TX_TXCC_MGNFS_MULT_100_j 0x0000000B 0x001C0015
    R SERDES_10G0_TX_TXCC_MGNFS_MULT_111__TX_TXCC_MGNFS_MULT_110_j 0x0000000B 0x002A0023
    R SERDES_10G0_TX_TXCC_MGNHS_MULT_001__TX_TXCC_MGNHS_MULT_000_j 0x0000000B 0x001C001C
    R SERDES_10G0_TX_TXCC_MGNHS_MULT_011__TX_TXCC_MGNHS_MULT_010_j 0x0000000B 0x00240020
    R SERDES_10G0_TX_TXCC_MGNHS_MULT_101__TX_TXCC_MGNHS_MULT_100_j 0x0000000B 0x002C0028
    R SERDES_10G0_TX_TXCC_MGNHS_MULT_111__TX_TXCC_MGNHS_MULT_110_j 0x0000000B 0x00360033
    R SERDES_10G0_TX_TXCC_P1PRE_COEF_MULT__TX_TXCC_P0PRE_COEF_MULT_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_P3PRE_COEF_MULT__TX_TXCC_P2PRE_COEF_MULT_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_P5PRE_COEF_MULT__TX_TXCC_P4PRE_COEF_MULT_j 0x0000000B 0x000D0000
    R SERDES_10G0_TX_TXCC_P7PRE_COEF_MULT__TX_TXCC_P6PRE_COEF_MULT_j 0x0000000B 0x000D0010
    R SERDES_10G0_TX_TXCC_P9PRE_COEF_MULT__TX_TXCC_P8PRE_COEF_MULT_j 0x0000000B 0x00160010
    R SERDES_10G0_TX_TXCC_P1POST_COEF_MULT__TX_TXCC_P0POST_COEF_MULT_j 0x0000000B 0x00160022
    R SERDES_10G0_TX_TXCC_P3POST_COEF_MULT__TX_TXCC_P2POST_COEF_MULT_j 0x0000000B 0x0010001B
    R SERDES_10G0_TX_TXCC_P5POST_COEF_MULT__TX_TXCC_P4POST_COEF_MULT_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_TXCC_P7POST_COEF_MULT__TX_TXCC_P6POST_COEF_MULT_j 0x0000000B 0x001B0000
    R SERDES_10G0_TX_TXCC_P9POST_COEF_MULT__TX_TXCC_P8POST_COEF_MULT_j 0x0000000B 0x00000010
    R SERDES_10G0_DRV_DIAG_LANE_FCM_EN_SWAIT_TMR__DRV_DIAG_LANE_FCM_EN_TO_j 0x0000000B 0x000601F4
    R SERDES_10G0_DRV_DIAG_LANE_FCM_EN_TUNE__DRV_DIAG_LANE_FCM_EN_MGN_TMR_j 0x0000000B 0x08C40096
    R SERDES_10G0_DRV_DIAG_RCVDET_TUNE__DRV_DIAG_LFPS_CTRL_j 0x0000000B 0x000C000F
    R SERDES_10G0_DRV_DIAG_TX_DRV_j 0x0000000B 0x000000B3
    R SERDES_10G0_XCVR_DIAG_XCAL_PWRI_OVRD__XCVR_DIAG_PWRI_TMR_j 0x0000000B 0x04240505
    R SERDES_10G0_XCVR_DIAG_XDP_PWRI_OVRD__XCVR_DIAG_XCAL_PWRI_STAT_j 0x0000000B 0x012400A6
    R SERDES_10G0_XCVR_DIAG_PLLDRC_CTRL__XCVR_DIAG_XDP_PWRI_STAT_j 0x0000000B 0x0013003B
    R SERDES_10G0_XCVR_DIAG_HSCLK_DIV__XCVR_DIAG_HSCLK_SEL_j 0x0000000B 0x00030000
    R SERDES_10G0_XCVR_DIAG_RXCLK_CTRL__XCVR_DIAG_TXCLK_CTRL_j 0x0000000B 0x40000000
    R SERDES_10G0_XCVR_DIAG_PSC_OVRD__XCVR_DIAG_BIDI_CTRL_j 0x0000000B 0x000600FF
    R SERDES_10G0_XCVR_DIAG_XCVR_CLK_CTRL__XCVR_DIAG_RST_DIAG_j 0x0000000B 0x000D0003
    R SERDES_10G0_XCVR_DIAG_DCYA_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_PSC_A1__TX_PSC_A0_j 0x0000000B 0x04AF00F3
    R SERDES_10G0_TX_PSC_A3__TX_PSC_A2_j 0x0000000B 0x04A204A2
    R SERDES_10G0_TX_PSC_A5__TX_PSC_A4_j 0x0000000B 0x00000880
    R SERDES_10G0_TX_PSC_RDY__TX_PSC_CAL_j 0x0000000B 0x00A000A0
    R SERDES_10G0_TX_RCVDET_OVRD__TX_RCVDET_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_RCVDET_ST_TMR__TX_RCVDET_EN_TMR_j 0x0000000B 0x09C40000
    R SERDES_10G0_TX_BIST_UDDWR__TX_BIST_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_BIST_SEED1__TX_BIST_SEED0_j 0x0000000B 0x00000000
    R SERDES_10G0_TX_DIAG_SFIFO_TMR__TX_DIAG_SFIFO_CTRL_j 0x0000000B 0x060C0004
    R SERDES_10G0_TX_DIAG_ELEC_IDLE_j 0x0000000B 0x00004433
    R SERDES_10G0_TX_DIAG_RST_DIAG_j 0x0000000B 0x001F0000
    R SERDES_10G0_TX_DIAG_ACYA__TX_DIAG_DCYA_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_PSC_A1__RX_PSC_A0_j 0x0000000B 0x091D091D
    R SERDES_10G0_RX_PSC_A3__RX_PSC_A2_j 0x0000000B 0x01000900
    R SERDES_10G0_RX_PSC_A5__RX_PSC_A4_j 0x0000000B 0x00001000
    R SERDES_10G0_RX_PSC_RDY__RX_PSC_CAL_j 0x0000000B 0x0000010F
    R SERDES_10G0_RX_SDCAL0_OVRD__RX_SDCAL0_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SDCAL0_TUNE__RX_SDCAL0_START_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SDCAL0_ITER_TMR__RX_SDCAL0_INIT_TMR_j 0x0000000B 0x007D0019
    R SERDES_10G0_RX_SDCAL1_OVRD__RX_SDCAL1_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SDCAL1_TUNE__RX_SDCAL1_START_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SDCAL1_ITER_TMR__RX_SDCAL1_INIT_TMR_j 0x0000000B 0x007D0019
    R SERDES_10G0_RX_SAMP_DAC_CTRL_j 0x0000000B 0x00000014
    R SERDES_10G0_RX_SLC_IPP_STAT__RX_SLC_CTRL_j 0x0000000B 0x00000001
    R SERDES_10G0_RX_SLC_IPM_STAT__RX_SLC_IPP_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SLC_QPP_STAT__RX_SLC_IPM_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SLC_QPM_STAT__RX_SLC_QPP_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SLC_EPP_STAT__RX_SLC_QPM_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SLC_EPM_STAT__RX_SLC_EPP_OVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_SLC_INIT_TMR__RX_SLC_EPM_OVRD_j 0x0000000B 0x00100000
    R SERDES_10G0_RX_SLC_DIAG_CTRL__RX_SLC_RUN_TMR_j 0x0000000B 0x0000A000
    R SERDES_10G0_RX_SLC_DIS_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_CDRLF_CNFG2__RX_CDRLF_CNFG_j 0x0000000B 0x2A33018C
    R SERDES_10G0_RX_CDRLF_MGN_DIAG__RX_CDRLF_CNFG3_j 0x0000000B 0x00000003
    R SERDES_10G0_RX_CDRLF_FPL_TMR1__RX_CDRLF_FPL_TMR0_j 0x0000000B 0x07310071
    R SERDES_10G0_RX_SIGDET_HL_DLY_TMR__RX_SIGDET_HL_FILT_TMR_j 0x0000000B 0x0000000C
    R SERDES_10G0_RX_SIGDET_HL_INIT_TMR__RX_SIGDET_HL_MIN_TMR_j 0x0000000B 0x00280000
    R SERDES_10G0_RX_SIGDET_LH_DLY_TMR__RX_SIGDET_LH_FILT_TMR_j 0x0000000B 0x00000004
    R SERDES_10G0_RX_SIGDET_LH_INIT_TMR__RX_SIGDET_LH_MIN_TMR_j 0x0000000B 0x00280000
    R SERDES_10G0_RX_LFPSDET_NS_CNT__RX_LFPSDET_MD_CNT_j 0x0000000B 0x00000005
    R SERDES_10G0_RX_LFPSDET_MP_CNT__RX_LFPSDET_RD_CNT_j 0x0000000B 0x00070007
    R SERDES_10G0_RX_LFPSDET_DIAG_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_EYESURF_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_EYESURF_TMR_DELHIGH__RX_EYESURF_TMR_DELLOW_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_EYESURF_TMR_TESTHIGH__RX_EYESURF_TMR_TESTLOW_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_EYESURF_EW_COORD__RX_EYESURF_NS_COORD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_EYESURF_ERRCNT_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_BIST_SYNCCNT__RX_BIST_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_BIST_ERRCNT__RX_BIST_UDDWR_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_PTXEQSM_EQENM_EVAL__RX_REE_PTXEQSM_CTRL_j 0x0000000B 0x3BC70000
    R SERDES_10G0_RX_REE_PTXEQSM_PEVAL_TMR__RX_REE_PTXEQSM_EQENM_PEVAL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_PTXEQSM_MAX_EVAL_CNT__RX_REE_PTXEQSM_TIMEOUT_TMR_j 0x0000000B 0x003F30D4
    R SERDES_10G0_RX_REE_GCSM1_EQENM_PH1__RX_REE_GCSM1_CTRL_j 0x0000000B 0x03C70009
    R SERDES_10G0_RX_REE_GCSM1_START_TMR__RX_REE_GCSM1_EQENM_PH2_j 0x0000000B 0x000001C7
    R SERDES_10G0_RX_REE_GCSM1_RUN_PH2_TMR__RX_REE_GCSM1_RUN_PH1_TMR_j 0x0000000B 0x009D0F43
    R SERDES_10G0_RX_REE_GCSM2_EQENM_PH1__RX_REE_GCSM2_CTRL_j 0x0000000B 0x00800009
    R SERDES_10G0_RX_REE_GCSM2_START_TMR__RX_REE_GCSM2_EQENM_PH2_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_GCSM2_RUN_PH2_TMR__RX_REE_GCSM2_RUN_PH1_TMR_j 0x0000000B 0x0000FFFF
    R SERDES_10G0_RX_REE_PERGCSM_EQENM_PH1__RX_REE_PERGCSM_CTRL_j 0x0000000B 0x03C7000D
    R SERDES_10G0_RX_REE_PERGCSM_START_TMR__RX_REE_PERGCSM_EQENM_PH2_j 0x0000000B 0x1E8501C7
    R SERDES_10G0_RX_REE_PERGCSM_RUN_PH2_TMR__RX_REE_PERGCSM_RUN_PH1_TMR_j 0x0000000B 0x009D009D
    R SERDES_10G0_RX_REE_U3GCSM_EQENM_PH1__RX_REE_U3GCSM_CTRL_j 0x0000000B 0x03C70009
    R SERDES_10G0_RX_REE_U3GCSM_START_TMR__RX_REE_U3GCSM_EQENM_PH2_j 0x0000000B 0x012501C7
    R SERDES_10G0_RX_REE_U3GCSM_RUN_PH2_TMR__RX_REE_U3GCSM_RUN_PH1_TMR_j 0x0000000B 0x009D07A2
    R SERDES_10G0_RX_REE_ANAENSM_DEL_TMR_j 0x0000000B 0x00000064
    R SERDES_10G0_RX_REE_TXPOST_CODE_CTRL__RX_REE_TXPOST_CTRL_j 0x0000000B 0x00000800
    R SERDES_10G0_RX_REE_TXPOST_LTHR__RX_REE_TXPOST_UTHR_j 0x0000000B 0x00060008
    R SERDES_10G0_RX_REE_TXPOST_COVRD0__RX_REE_TXPOST_IOVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_TXPOST_DIAG__RX_REE_TXPOST_COVRD1_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_TXPRE_OVRD__RX_REE_TXPRE_CTRL_j 0x0000000B 0x00000D00
    R SERDES_10G0_RX_REE_TXPRE_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_PEAK_CODE_CTRL__RX_REE_PEAK_CTRL_j 0x0000000B 0x2A200F01
    R SERDES_10G0_RX_REE_PEAK_LTHR__RX_REE_PEAK_UTHR_j 0x0000000B 0x01FA0004
    R SERDES_10G0_RX_REE_PEAK_COVRD0__RX_REE_PEAK_IOVRD_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_PEAK_DIAG__RX_REE_PEAK_COVRD1_j 0x0000000B 0x00200000
    R SERDES_10G0_RX_REE_ATTEN_THR__RX_REE_ATTEN_CTRL_j 0x0000000B 0x0C020005
    R SERDES_10G0_RX_REE_ATTEN_OVRD__RX_REE_ATTEN_CNT_j 0x0000000B 0x00002100
    R SERDES_10G0_RX_REE_ATTEN_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_TAP1_OVRD__RX_REE_TAP1_CTRL_j 0x0000000B 0x00000400
    R SERDES_10G0_RX_REE_TAP1_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_TAP2_OVRD__RX_REE_TAP2_CTRL_j 0x0000000B 0x00000400
    R SERDES_10G0_RX_REE_TAP2_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_TAP3_OVRD__RX_REE_TAP3_CTRL_j 0x0000000B 0x00000400
    R SERDES_10G0_RX_REE_TAP3_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_LFEQ_OVRD__RX_REE_LFEQ_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_LFEQ_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_VGA_GAIN_OVRD__RX_REE_VGA_GAIN_CTRL_j 0x0000000B 0x00001701
    R SERDES_10G0_RX_REE_VGA_GAIN_TGT_DIAG__RX_REE_VGA_GAIN_DIAG_j 0x0000000B 0x0000000A
    R SERDES_10G0_RX_REE_OFF_COR_OVRD__RX_REE_OFF_COR_CTRL_j 0x0000000B 0x00000001
    R SERDES_10G0_RX_REE_OFF_COR_DIAG_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_REE_SC_COR_TCNT__RX_REE_SC_COR_WCNT_j 0x0000000B 0x0004000A
    R SERDES_10G0_RX_REE_TAP1_CLIP__RX_REE_ADDR_CFG_j 0x0000000B 0x00190101
    R SERDES_10G0_RX_REE_CTRL_DATA_MASK__RX_REE_TAP2TON_CLIP_j 0x0000000B 0x40000019
    R SERDES_10G0_RX_REE_DIAG_CTRL__RX_REE_FIFO_DIAG_j 0x0000000B 0x00724000
    R SERDES_10G0_RX_REE_SMGM_CTRL1__RX_REE_TXEQEVAL_CTRL_j 0x0000000B 0x06F60000
    R SERDES_10G0_RX_REE_TXEQEVAL_PRE__RX_REE_SMGM_CTRL2_j 0x0000000B 0x00004606
    R SERDES_10G0_RX_REE_TXEQEVAL_POST_j 0x0000000B 0x00000000
    R SERDES_10G0_XCVR_CMSMT_TEST_CLK_SEL__XCVR_CMSMT_CLK_FREQ_MSMT_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_XCVR_CMSMT_TEST_CLK_CNT_VALUE__XCVR_CMSMT_REF_CLK_TMR_VALUE_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_DIAG_DFE_AMP_TUNE__RX_DIAG_DFE_CTRL_j 0x0000000B 0x4DDD0000
    R SERDES_10G0_RX_DIAG_DFE_AMP_TUNE_3__RX_DIAG_DFE_AMP_TUNE_2_j 0x0000000B 0x00000C01
    R SERDES_10G0_RX_DIAG_NQST_CTRL__RX_DIAG_REE_DAC_CTRL_j 0x0000000B 0x00980004
    R SERDES_10G0_RX_DIAG_LFEQ_TUNE_j 0x0000000B 0x000000E4
    R SERDES_10G0_RX_DIAG_SH_SIGDET__RX_DIAG_SIGDET_TUNE_j 0x0000000B 0x11101001
    R SERDES_10G0_RX_DIAG_SD_TEST_j 0x0000000B 0x00000000
    R SERDES_10G0_RX_DIAG_SH_SLC_IPP__RX_DIAG_SAMP_CTRL_j 0x0000000B 0x45430001
    R SERDES_10G0_RX_DIAG_SH_SLC_QPP__RX_DIAG_SH_SLC_IPM_j 0x0000000B 0x53514706
    R SERDES_10G0_RX_DIAG_SH_SLC_EPP__RX_DIAG_SH_SLC_QPM_j 0x0000000B 0x040B4913
    R SERDES_10G0_RX_DIAG_SH_SLC_EPM_j 0x0000000B 0x00004D4D
    R SERDES_10G0_RX_DIAG_PI_CAP__RX_DIAG_PI_RATE_j 0x0000000B 0x00000010
    R SERDES_10G0_RX_DIAG_PI_TUNE_j 0x0000000B 0x00000061
    R SERDES_10G0_RX_DIAG_RST_DIAG__RX_DIAG_LPBK_CTRL_j 0x0000000B 0x003F0000
    R SERDES_10G0_RX_DIAG_ACYA__RX_DIAG_DCYA_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PIPE_CMN_CTRL2__PHY_PIPE_CMN_CTRL1 0x0000000B 0xBD510400
    R SERDES_10G0_PHY_PIPE_COM_LOCK_CFG2__PHY_PIPE_COM_LOCK_CFG1 0x0000000B 0x08204400
    R SERDES_10G0_PHY_PIPE_LANE_DSBL__PHY_PIPE_EIE_LOCK_CFG 0x0000000B 0x0000137F
    R SERDES_10G0_PHY_PIPE_RX_ELEC_IDLE_DLY__PHY_PIPE_RCV_DET_INH 0x0000000B 0x3C963D09
    R SERDES_10G0_PHY_ISO_CMN_CTRL 0x0000000B 0x00001001
    R SERDES_10G0_PHY_STATE_CHG_TIMEOUT 0x0000000B 0x000030D4
    R SERDES_10G0_PHY_AUTO_CFG_SPDUP 0x0000000B 0x00000000
    R SERDES_10G0_PHY_REFCLK_DET_THRES_HIGH__PHY_REFCLK_DET_THRES_LOW 0x0000000B 0x274201C2
    R SERDES_10G0_PHY_REFCLK_DET_OP_DELAY__PHY_REFCLK_DET_INTERVAL 0x0000000B 0x106403E8
    R SERDES_10G0_PHY_REFCLK_DET_ISO_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PIPE_ISO_TX_LPC_LO__PHY_PIPE_ISO_TX_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PCS_ISO_TX_DMPH_LO__PHY_PIPE_ISO_TX_LPC_HI_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PIPE_ISO_TX_FSLF__PHY_PIPE_ISO_TX_DMPH_HI_j 0x0000000B 0x37130000
    R SERDES_10G0_PHY_PCS_ISO_TX_DATA_HI__PHY_PCS_ISO_TX_DATA_LO_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PIPE_ISO_RX_EQ_EVAL__PHY_PCS_ISO_RX_CTRL_j 0x0000000B 0x00400010
    R SERDES_10G0_PHY_PCS_ISO_LINK_CTRL__PHY_ISO_LINK_CFG_j 0x0000000B 0x00230000
    R SERDES_10G0_PHY_PIPE_ISO_USB_BER_CNT_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PCS_ISO_RX_DATA_HI__PHY_PCS_ISO_RX_DATA_LO_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_ETH_ISO_MAC_CLK_DIV__PHY_ETH_ISO_MAC_CLK_CFG_j 0x0000000B 0x00810000
    R SERDES_10G0_PHY_INTERRUPT_STS_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PMA_CMN_CTRL2__PHY_PMA_CMN_CTRL1 0x0000000B 0x00490011
    R SERDES_10G0_PHY_PMA_PLL_RAW_CTRL__PHY_PMA_SSM_STATE 0x0000000B 0x0003001B
    R SERDES_10G0_PHY_PMA_ISO_PLL_CTRL0__PHY_PMA_ISO_CMN_CTRL 0x0000000B 0x00030001
    R SERDES_10G0_PHY_PMA_ISO_PLL_CTRL1 0x0000000B 0x00001124
    R SERDES_10G0_PHY_PMA_PLL0_SM_STATE 0x0000000B 0x00DB0000
    R SERDES_10G0_PHY_PMA_PLL1_SM_STATE 0x0000000B 0x00000300
    R SERDES_10G0_PHY_PMA_ISOLATION_CTRL 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PMA_XCVR_LPBK__PHY_PMA_XCVR_CTRL_j 0x0000000B 0x00000010
    R SERDES_10G0_PHY_PMA_ISO_XCVR_CTRL_j 0x0000000B 0x8008C3C3
    R SERDES_10G0_PHY_PMA_ISO_TX_LPC_HI__PHY_PMA_ISO_TX_LPC_LO_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PMA_ISO_TX_DMPH_HI__PHY_PMA_ISO_TX_DMPH_LO_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PMA_ISO_TX_MGN__PHY_PMA_ISO_TX_FSLF_j 0x0000000B 0x00003713
    R SERDES_10G0_PHY_PMA_ISO_PWRST_CTRL__PHY_PMA_ISO_LINK_MODE_j 0x0000000B 0x0000C000
    R SERDES_10G0_PHY_PMA_ISO_RX_EQ_CTRL_j 0x0000000B 0x00000000
    R SERDES_10G0_PHY_PMA_ISO_DATA_HI__PHY_PMA_ISO_DATA_LO_j 0x0000000B 0x00073D1B
    R SERDES_10G0_PHY_PMA_PSM_STATE_HI__PHY_PMA_PSM_STATE_LO_j 0x0000000B 0x12000001
    

     the   cpsw0_sgmii5  status  reg show it not linked up / auto-neg never completed

    then code end in while loop wait for   sgmii  status reg  set.

    There may be one question need to be confirmed from  you side first

    Can  cpsw9g MAC5 config as  sgmii mode  ,   connect PHY like RTL9010aa ? what's it difference  with mac2?

  • Hi,

    Sorry for the delay in response.

    There is functionally no difference between Port2 and Port5, both can act as SGMII ports.

    Since you have Port 2 working and both Port 2 and Port 5 use the same PHY,  I am guessing that you have all the basics (driver, configuration) done right.

    Few questions and actions for you

    1. Have you checked the pinmuxing ? Recently another customer had an issue with Port 5(though with SGMII) and the culprit was pinmuxing. Please see this thread.

    2. Can you provide the Ethernet Firmware UART output ?

    3. Do you have Linux running on A72 ? Have you disabled the SERDES there ? Take a look at this link which explains how to enable QSGMII on J721E. Use it as a reference. A customer used this as a reference to enable SGMII. See this E2E

    Regards

    Vineet

  • 1.. we have checked  pinmux.  I have deleted the dp pin config in pinmux.c .since it is  conflict with  sgmii5.

    pinmuxBoardCfg_t gJ721E_WkupPinmuxDataHpb[] =
    {
    // {0, gMcu_fss0_hpbPinCfg},
    {PINMUX_END}
    };

    2.  log see below file

    9gmac5.txt
    =======================================================
                CPSW Ethernet Firmware
    =======================================================
    CPSW_9G Test on MAIN NAVSS
    Enet_open: cpsw9g: features: 0x00000002
    Enet_open: cpsw9g: errata  : 0x00000000
    CpswMacPort_configSgmii: MAC 5: Configuring SGMII in SGMII_WITH_PHY mode
    EnetPhy_setNextState: PHY 1: INIT -> FINDING (20 ticks)
    EnetPhy_setNextState: PHY 1: FINDING -> FOUND (0 ticks)
    EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx'
    EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx' : OK
    EnetPhy_open: PHY 1: open
    PHY 0 is alive
    PHY 1 is alive
    PHY 2 is alive
    PHY 3 is alive
    
    ETHFW Version   : 0.01.01
    ETHFW Build Date: Oct 15, 2021
    ETHFW Build Time: 11:00:41
    ETHFW Commit SHA:
    
    EnetPhy_setNextState: PHY 1: FOUND -> RESET_WAIT (10 ticks)
    IPC_echo_test (core : mcu2_0) .....
    GenericPhy_isResetComplete: PHY 1: reset is complete
    Remote demo device (core : mcu2_0) .....
    EnetPhy_setNextState: PHY 1: RESET_WAIT -> ENABLE (0 ticks)
    EnetPhy_enableState: PHY 1: enable
    RTL9010AA_VA_Initial_Configuration: PHY link state: 0
    RTL9010AA_VA_Initial_Configuration: PHY bmcr state: 320
    RTL9010AA_VA_Initial_Configuration: PHY phycr state: 0
    RTL9010AA_VA_Initial_Configuration: PHY link state: 4
    RTL9010AA_VA_Initial_Configuration: PHY bmcr state: 320
    RTL9010AA_VA_Initial_Configuration: PHY physr2 state: 12288
    EnetPhy_enableState: PHY 1: req caps: FD1000 HD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 1: PHY caps: FD1000
    EnetPhy_enableState: PHY 1: MAC caps: FD1000 FD100 HD100 FD10 HD10
    EnetPhy_enableState: PHY 1: refined caps: FD1000
    EnetPhy_enableState: PHY 1: PHY is not NWAY-capable
    EnetPhy_enableState: PHY 1: falling back to manual mode
    EnetPhy_enableState: PHY 1: new link caps: FD1000
    EnetPhy_enableState: PHY 1: manual setup
    EnetPhy_setNextState: PHY 1: ENABLE -> LINK_WAIT (50 ticks)
    EnetPhy_setNextState: PHY 1: LINK_WAIT -> LINKED (0 ticks)
    
    

    3. we haven't  run linux at all .we use CCS , only run sysfw  and ethfw code on R5f. we never run A72 at all.

  • Hi,

    Sorry for the delay. Since you mentioned that you are running CCS, can you run the debug gels in <SDK_INSTALL_DIR>/pdk/packages/ti/drv/enet/tools/debug_gels

    Please run the following GEL files and provide output

    1. cpsw_sgmii_diag.gel

    2. cpsw_enetctrl_cfg.gel

    3. cpsw_print_reg.gel

    Regards

    Vineet

  • MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x02560000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x02420000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000

    Hi Vineet,

         Thanks for your reply. I got the output via GEL, as following:

    1. cpsw_sgmii_diag.gel

    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Control
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG ENABLE = 1
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG RESTART = 0
    MAIN_Cortex_R5_0_0: GEL Output: FAST Link Timer = 0
    MAIN_Cortex_R5_0_0: GEL Output: Next Page Loaded = 0
    MAIN_Cortex_R5_0_0: GEL Output: Loopback = 0
    MAIN_Cortex_R5_0_0: GEL Output: Master Mode = 0
    MAIN_Cortex_R5_0_0: GEL Output: Test Pattern Enable = 0
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Status
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 0
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG Complete = 0
    MAIN_Cortex_R5_0_0: GEL Output: Next Page Received = 0
    MAIN_Cortex_R5_0_0: GEL Output: SERDES DPLL Locked = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Advertised Ability
    MAIN_Cortex_R5_0_0: GEL Output: Link Speed = 1Gbps
    MAIN_Cortex_R5_0_0: GEL Output: Dupexity = Full Duplex
    MAIN_Cortex_R5_0_0: GEL Output: AUTO-NEG ACK = 0
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Link Partner Advertised Ability
    MAIN_Cortex_R5_0_0: GEL Output: Link Speed = 10Mbps
    MAIN_Cortex_R5_0_0: GEL Output: Dupexity = Half Duplex
    MAIN_Cortex_R5_0_0: GEL Output: AUTO-NEG ACK = 0
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Hold signals
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: lock = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_signal_detect = 1
    MAIN_Cortex_R5_0_0: GEL Output: an_sync_status = 0
    MAIN_Cortex_R5_0_0: GEL Output: carrier_detect = 1
    MAIN_Cortex_R5_0_0: GEL Output: sync_status = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_k28_5 = 0
    MAIN_Cortex_R5_0_0: GEL Output: idle_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: ability_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: consistency_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: acknowledge_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_invalid = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_link_timer_done = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Sync Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: LOSS_OF_SYNC = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic AutoNeg Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: LINK_OK = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMPLETE_ACKNOWLEDGE = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACKNOWLEDGE_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_DISABLE_LINK_OK = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESTART = 0
    MAIN_Cortex_R5_0_0: GEL Output: NEXT_PAGE_WAIT = 0
    MAIN_Cortex_R5_0_0: GEL Output: ABILITY_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_ENABLE = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESET = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXOS Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CARRIER_EXTEND = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_OF_PACKET_EXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: ALIGN_ERR_START = 0
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_BY_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: (START_OF_PACKET or TX_DATA) with tx_oset_indicate = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: XMIT_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD2_NOEXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_O F_PACKET_NOEXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE = 1
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG = 0
    MAIN_Cortex_R5_0_0: GEL Output: (!t_rst_n || (xmit_change && tx_oset_indicate && !tx_even)) = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXCFG Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_IXB = 1
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DISP = 1
    MAIN_Cortex_R5_0_0: GEL Output: DATA_GO = 0
    MAIN_Cortex_R5_0_0: GEL Output: SPECIAL_GO = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2D = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2C = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2B = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1D = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1C = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1B = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1A = 0
    MAIN_Cortex_R5_0_0: GEL Output: GEN_CODE_GROUP = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Lower Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END_EXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRR_EXTEND = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRI_RRI = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: FALSE_CARRIER = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_INVALID = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_D = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CD = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CC = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CB = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_K = 0
    MAIN_Cortex_R5_0_0: GEL Output: WAIT_FOR_K = 0
    MAIN_Cortex_R5_0_0: GEL Output: LINK_FAILED = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Upper Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_ERR = 0
    MAIN_Cortex_R5_0_0: GEL Output: PACKET_BURST_RRS = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES MMR Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 = Enet Switch Q/SGMII Lane 5
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES Lane Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANECTL = 0x70800000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANEDIV = 0x00010002
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANALIGN = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANESTS = 0x00000002
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Control
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG ENABLE = 1
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG RESTART = 0
    MAIN_Cortex_R5_0_0: GEL Output: FAST Link Timer = 0
    MAIN_Cortex_R5_0_0: GEL Output: Next Page Loaded = 0
    MAIN_Cortex_R5_0_0: GEL Output: Loopback = 0
    MAIN_Cortex_R5_0_0: GEL Output: Master Mode = 0
    MAIN_Cortex_R5_0_0: GEL Output: Test Pattern Enable = 0
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Status
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 0
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: AUTONEG Complete = 0
    MAIN_Cortex_R5_0_0: GEL Output: Next Page Received = 0
    MAIN_Cortex_R5_0_0: GEL Output: SERDES DPLL Locked = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Advertised Ability
    MAIN_Cortex_R5_0_0: GEL Output: Link Speed = 1Gbps
    MAIN_Cortex_R5_0_0: GEL Output: Dupexity = Full Duplex
    MAIN_Cortex_R5_0_0: GEL Output: AUTO-NEG ACK = 0
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Link Partner Advertised Ability
    MAIN_Cortex_R5_0_0: GEL Output: Link Speed = 10Mbps
    MAIN_Cortex_R5_0_0: GEL Output: Dupexity = Half Duplex
    MAIN_Cortex_R5_0_0: GEL Output: AUTO-NEG ACK = 0
    MAIN_Cortex_R5_0_0: GEL Output: Link Up = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Hold signals
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: lock = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_signal_detect = 1
    MAIN_Cortex_R5_0_0: GEL Output: an_sync_status = 0
    MAIN_Cortex_R5_0_0: GEL Output: carrier_detect = 1
    MAIN_Cortex_R5_0_0: GEL Output: sync_status = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_k28_5 = 0
    MAIN_Cortex_R5_0_0: GEL Output: idle_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: ability_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: consistency_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: acknowledge_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_invalid = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_link_timer_done = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Sync Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_2 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: LOSS_OF_SYNC = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic AutoNeg Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: LINK_OK = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMPLETE_ACKNOWLEDGE = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACKNOWLEDGE_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_DISABLE_LINK_OK = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESTART = 0
    MAIN_Cortex_R5_0_0: GEL Output: NEXT_PAGE_WAIT = 0
    MAIN_Cortex_R5_0_0: GEL Output: ABILITY_DETECT = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_ENABLE = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESET = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXOS Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CARRIER_EXTEND = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_OF_PACKET_EXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: ALIGN_ERR_START = 0
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_BY_1 = 0
    MAIN_Cortex_R5_0_0: GEL Output: (START_OF_PACKET or TX_DATA) with tx_oset_indicate = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: XMIT_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD3 = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD2_NOEXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_O F_PACKET_NOEXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE = 1
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG = 0
    MAIN_Cortex_R5_0_0: GEL Output: (!t_rst_n || (xmit_change && tx_oset_indicate && !tx_even)) = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXCFG Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_IXB = 1
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DISP = 1
    MAIN_Cortex_R5_0_0: GEL Output: DATA_GO = 0
    MAIN_Cortex_R5_0_0: GEL Output: SPECIAL_GO = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2D = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2C = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2B = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1D = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1C = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1B = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1A = 0
    MAIN_Cortex_R5_0_0: GEL Output: GEN_CODE_GROUP = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Lower Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END_EXT = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_DATA = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRR_EXTEND = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRI_RRI = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR = 0
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: FALSE_CARRIER = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_INVALID = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_D = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CD = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CC = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CB = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_K = 0
    MAIN_Cortex_R5_0_0: GEL Output: WAIT_FOR_K = 0
    MAIN_Cortex_R5_0_0: GEL Output: LINK_FAILED = 1
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Upper Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_ERR = 0
    MAIN_Cortex_R5_0_0: GEL Output: PACKET_BURST_RRS = 0
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES MMR Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 = Enet Switch Q/SGMII Lane 5
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES Lane Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANECTL = 0x70800000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANEDIV = 0x00010002
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANALIGN = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANESTS = 0x00000002

    2. cpsw_enetctrl_cfg.gel

    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:      CPSW2G MAC Mode Config   
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RMII
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:      CPSW9G MAC Mode Config   
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 1: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 2: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 3: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 4: Mode: SGMII
    MAIN_Cortex_R5_0_0: GEL Output: Port 5: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 6: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output: Port 7: Mode: RGMII, RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:   BOARD Verify ENET CTRL  
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: CPSW2G Port 0
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: Mode: RGMII, Actual: Mode: RMII
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: RGMII-ID:Disabled, Actual: RGMII-ID:Enabled
    MAIN_Cortex_R5_0_0: GEL Output:
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 0
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 1
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 2
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 3
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 4
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 5
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 6
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 7
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: Mode: RMII, Actual: Mode: RGMII 

    3. cpsw_print_reg.gel

    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x02560000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x02420000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000

    For above, please help up to analyze. And please contact us if there is anything else to check or modify.

    Thank you for your help and looking forward to your reply.

    Regards,

    Lan

  • Hi,

    Let's try to isolate PHY vs MAC issues. From the logs, I do not see anything obvious. Would it be possible for you to port the ENET loopback application to your HW ? <SDK_INSTALL_DIR>/pdk/packages/ti/drv/enet/examples/enet_loopback_test ?

    The ENET changes are the same, you only have to do the app changes. The idea would be to first check the loopback at MAC level to verify that the configuration is correct, and then do the loopback at PHY level to make sure that driver is setup correctly. All of this assumes that there is no pinmux issue.

    Regards

    Vineet

  • Hi Vineet,

    Thank you for your reply. I tried to run enet_loopback_test and the log is following:

    ============================= 
    Enet Loopback: Iteration 1 
    =============================
    Enabling clocks!
    CPSW_9G Test on MAIN NAVSS
    Enet_open: cpsw9g: features: 0x00000002
    Enet_open: cpsw9g: errata  : 0x00000000
    EnetBoard_setupPorts: 1 of 1 ports configurations found
    CpswMacPort_configSgmii: MAC 5: Configuring SGMII in SGMII_WITH_PHY mode
    EnetPhy_setNextState: PHY 1: INIT -> FINDING (20 ticks)
    EnetPhy_setNextState: PHY 1: FINDING -> FOUND (0 ticks)
    EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx'
    EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx' : OK
    EnetPhy_open: PHY 1: open
    initQs() txFreePktInfoQ initialized with 128 pkts
    Host MAC address: 70:ff:76:1d:92:c2
    PHY 0 is alive
    PHY 1 is alive
    PHY 2 is alive
    PHY 3 is alive
    EnetPhy_setNextState: PHY 1: FOUND -> RESET_WAIT (10 ticks)
    GenericPhy_isResetComplete: PHY 1: reset is complete
    EnetPhy_setNextState: PHY 1: RESET_WAIT -> ENABLE (0 ticks)
    EnetPhy_enableState: PHY 1: enable
    EnetPhy_enableState: PHY 1: req caps: FD1000 
    EnetPhy_enableState: PHY 1: PHY caps: FD1000 
    EnetPhy_enableState: PHY 1: MAC caps: FD1000 FD100 HD100 FD10 HD10 
    EnetPhy_enableState: PHY 1: refined caps: FD1000 
    EnetPhy_enableState: PHY 1: PHY is not NWAY-capable
    EnetPhy_enableState: PHY 1: setup loopback
    EnetPhy_setupManual: PHY 1: requested mode: 1 Gbps full-duplex
    EnetPhy_setNextState: PHY 1: ENABLE -> LOOPBACK (0 ticks)

    And  I got the output via GEL, as following:

    1. cpsw_sgmii_diag.gel

    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Control 
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG ENABLE      = 1
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG RESTART     = 0
    MAIN_Cortex_R5_0_0: GEL Output:   FAST Link Timer     = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Next Page Loaded    = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Loopback            = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Master Mode         = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Test Pattern Enable = 0
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Status 
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 0
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG ERROR       = 0
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG Complete    = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Next Page Received  = 0
    MAIN_Cortex_R5_0_0: GEL Output:   SERDES DPLL Locked  = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Advertised Ability  
    MAIN_Cortex_R5_0_0: GEL Output:   Link Speed          = 1Gbps
    MAIN_Cortex_R5_0_0: GEL Output:   Dupexity            = Full Duplex
    MAIN_Cortex_R5_0_0: GEL Output:   AUTO-NEG ACK        = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Link Partner Advertised Ability 
    MAIN_Cortex_R5_0_0: GEL Output:   Link Speed          = 10Mbps
    MAIN_Cortex_R5_0_0: GEL Output:   Dupexity            = Half Duplex
    MAIN_Cortex_R5_0_0: GEL Output:   AUTO-NEG ACK        = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Hold signals
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: lock              = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_signal_detect   = 1
    MAIN_Cortex_R5_0_0: GEL Output: an_sync_status    = 0
    MAIN_Cortex_R5_0_0: GEL Output: carrier_detect    = 1
    MAIN_Cortex_R5_0_0: GEL Output: sync_status       = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_k28_5      = 0
    MAIN_Cortex_R5_0_0: GEL Output: idle_match        = 0
    MAIN_Cortex_R5_0_0: GEL Output: ability_match     = 0
    MAIN_Cortex_R5_0_0: GEL Output: consistency_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: acknowledge_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_invalid    = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_link_timer_done = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Sync Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_1  = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_3   = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_2   = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_2   = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_1   = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_1   = 0
    MAIN_Cortex_R5_0_0: GEL Output: LOSS_OF_SYNC     = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic AutoNeg Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: LINK_OK               = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DETECT           = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMPLETE_ACKNOWLEDGE  = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACKNOWLEDGE_DETECT    = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_DISABLE_LINK_OK    = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESTART            = 0
    MAIN_Cortex_R5_0_0: GEL Output: NEXT_PAGE_WAIT        = 0
    MAIN_Cortex_R5_0_0: GEL Output: ABILITY_DETECT        = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_ENABLE             = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESET              = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXOS Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CARRIER_EXTEND                                              = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_OF_PACKET_EXT                                           = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR                                               = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_ERROR                                                 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ALIGN_ERR_START                                             = 0
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_BY_1                                                 = 0
    MAIN_Cortex_R5_0_0: GEL Output: (START_OF_PACKET or TX_DATA) with tx_oset_indicate          = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET                                             = 0
    MAIN_Cortex_R5_0_0: GEL Output: XMIT_DATA                                                   = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD3                                                        = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD2_NOEXT                                                  = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_O F_PACKET_NOEXT                                        = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA                                                     = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE                                                        = 1
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG                                                      = 0
    MAIN_Cortex_R5_0_0: GEL Output: (!t_rst_n || (xmit_change && tx_oset_indicate && !tx_even)) = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXCFG Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_IXB       = 1
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DISP      = 1
    MAIN_Cortex_R5_0_0: GEL Output: DATA_GO        = 0
    MAIN_Cortex_R5_0_0: GEL Output: SPECIAL_GO     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2D     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2C     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2B     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2A     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1D     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1C     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1B     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1A     = 0
    MAIN_Cortex_R5_0_0: GEL Output: GEN_CODE_GROUP = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Lower Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END_EXT   = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_DATA         = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRR_EXTEND      = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRI_RRI         = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR   = 0
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END       = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: FALSE_CARRIER   = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_INVALID      = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_D          = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CD           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CC           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CB           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_K            = 0
    MAIN_Cortex_R5_0_0: GEL Output: WAIT_FOR_K      = 0
    MAIN_Cortex_R5_0_0: GEL Output: LINK_FAILED     = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Upper Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_ERR          = 0
    MAIN_Cortex_R5_0_0: GEL Output: PACKET_BURST_RRS    = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES MMR Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0           = Enet Switch Q/SGMII Lane 5
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES Lane Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANECTL       = 0x70800000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANEDIV       = 0x00010002
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANALIGN      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANESTS       = 0x00000002
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: | CPSWnG Port 5 |
    MAIN_Cortex_R5_0_0: GEL Output: =================
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Control 
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG ENABLE      = 1
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG RESTART     = 0
    MAIN_Cortex_R5_0_0: GEL Output:   FAST Link Timer     = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Next Page Loaded    = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Loopback            = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Master Mode         = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Test Pattern Enable = 0
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Status 
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 0
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG ERROR       = 0
    MAIN_Cortex_R5_0_0: GEL Output:   AUTONEG Complete    = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Next Page Received  = 0
    MAIN_Cortex_R5_0_0: GEL Output:   SERDES DPLL Locked  = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Advertised Ability  
    MAIN_Cortex_R5_0_0: GEL Output:   Link Speed          = 1Gbps
    MAIN_Cortex_R5_0_0: GEL Output:   Dupexity            = Full Duplex
    MAIN_Cortex_R5_0_0: GEL Output:   AUTO-NEG ACK        = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 1
    MAIN_Cortex_R5_0_0: GEL Output: SGMII Link Partner Advertised Ability 
    MAIN_Cortex_R5_0_0: GEL Output:   Link Speed          = 10Mbps
    MAIN_Cortex_R5_0_0: GEL Output:   Dupexity            = Half Duplex
    MAIN_Cortex_R5_0_0: GEL Output:   AUTO-NEG ACK        = 0
    MAIN_Cortex_R5_0_0: GEL Output:   Link Up             = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Hold signals
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: lock              = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_signal_detect   = 1
    MAIN_Cortex_R5_0_0: GEL Output: an_sync_status    = 0
    MAIN_Cortex_R5_0_0: GEL Output: carrier_detect    = 1
    MAIN_Cortex_R5_0_0: GEL Output: sync_status       = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_k28_5      = 0
    MAIN_Cortex_R5_0_0: GEL Output: idle_match        = 0
    MAIN_Cortex_R5_0_0: GEL Output: ability_match     = 0
    MAIN_Cortex_R5_0_0: GEL Output: consistency_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: acknowledge_match = 0
    MAIN_Cortex_R5_0_0: GEL Output: pcs_rx_invalid    = 1
    MAIN_Cortex_R5_0_0: GEL Output: r_link_timer_done = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic Sync Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2A = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_4  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_3  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_2  = 0
    MAIN_Cortex_R5_0_0: GEL Output: SYNC_ACQUIRED_1  = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_3   = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_2   = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_2   = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACQUIRE_SYNC_1   = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMMA_DETECT_1   = 0
    MAIN_Cortex_R5_0_0: GEL Output: LOSS_OF_SYNC     = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic AutoNeg Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: LINK_OK               = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DETECT           = 0
    MAIN_Cortex_R5_0_0: GEL Output: COMPLETE_ACKNOWLEDGE  = 0
    MAIN_Cortex_R5_0_0: GEL Output: ACKNOWLEDGE_DETECT    = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_DISABLE_LINK_OK    = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESTART            = 0
    MAIN_Cortex_R5_0_0: GEL Output: NEXT_PAGE_WAIT        = 0
    MAIN_Cortex_R5_0_0: GEL Output: ABILITY_DETECT        = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_ENABLE             = 0
    MAIN_Cortex_R5_0_0: GEL Output: AN_RESET              = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXOS Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CARRIER_EXTEND                                              = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_OF_PACKET_EXT                                           = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR                                               = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_ERROR                                                 = 0
    MAIN_Cortex_R5_0_0: GEL Output: ALIGN_ERR_START                                             = 0
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_BY_1                                                 = 0
    MAIN_Cortex_R5_0_0: GEL Output: (START_OF_PACKET or TX_DATA) with tx_oset_indicate          = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET                                             = 0
    MAIN_Cortex_R5_0_0: GEL Output: XMIT_DATA                                                   = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD3                                                        = 0
    MAIN_Cortex_R5_0_0: GEL Output: EPD2_NOEXT                                                  = 0
    MAIN_Cortex_R5_0_0: GEL Output: END_O F_PACKET_NOEXT                                        = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA                                                     = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE                                                        = 1
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG                                                      = 0
    MAIN_Cortex_R5_0_0: GEL Output: (!t_rst_n || (xmit_change && tx_oset_indicate && !tx_even)) = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic TXCFG Status
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_IXB       = 1
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_DISP      = 1
    MAIN_Cortex_R5_0_0: GEL Output: DATA_GO        = 0
    MAIN_Cortex_R5_0_0: GEL Output: SPECIAL_GO     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2D     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2C     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2B     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C2A     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1D     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1C     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1B     = 0
    MAIN_Cortex_R5_0_0: GEL Output: CONFIG_C1A     = 0
    MAIN_Cortex_R5_0_0: GEL Output: GEN_CODE_GROUP = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Lower Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END_EXT   = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_DATA         = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRR_EXTEND      = 0
    MAIN_Cortex_R5_0_0: GEL Output: TRI_RRI         = 0
    MAIN_Cortex_R5_0_0: GEL Output: TX_DATA_ERROR   = 0
    MAIN_Cortex_R5_0_0: GEL Output: EARLY_END       = 0
    MAIN_Cortex_R5_0_0: GEL Output: START_OF_PACKET = 0
    MAIN_Cortex_R5_0_0: GEL Output: FALSE_CARRIER   = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_INVALID      = 0
    MAIN_Cortex_R5_0_0: GEL Output: IDLE_D          = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CD           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CC           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_CB           = 0
    MAIN_Cortex_R5_0_0: GEL Output: RX_K            = 0
    MAIN_Cortex_R5_0_0: GEL Output: WAIT_FOR_K      = 0
    MAIN_Cortex_R5_0_0: GEL Output: LINK_FAILED     = 1
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SGMII Diagnostic RX SM Status Upper Bits
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: EXTEND_ERR          = 0
    MAIN_Cortex_R5_0_0: GEL Output: PACKET_BURST_RRS    = 0
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES MMR Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0           = Enet Switch Q/SGMII Lane 5
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW Port 5 - SERDES Lane Registers
    MAIN_Cortex_R5_0_0: GEL Output: --------------------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANECTL       = 0x70800000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANEDIV       = 0x00010002
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANALIGN      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SERDES4 Lane 0 LANESTS       = 0x00000002
    

    2.  cpsw_enetctrl_cfg.gel

    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:      CPSW2G MAC Mode Config   
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RMII
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:      CPSW9G MAC Mode Config   
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: Port 0: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 1: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 2: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 3: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 4: Mode: SGMII
    MAIN_Cortex_R5_0_0: GEL Output: Port 5: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 6: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: Port 7: Mode: RGMII, RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output:   BOARD Verify ENET CTRL  
    MAIN_Cortex_R5_0_0: GEL Output: ==============================
    MAIN_Cortex_R5_0_0: GEL Output: CPSW2G Port 0 
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: Mode: RGMII, Actual: Mode: RMII 
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: RGMII-ID:Disabled, Actual: RGMII-ID:Enabled 
    MAIN_Cortex_R5_0_0: GEL Output: 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 0 
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 1 
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 2 
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 3 
    MAIN_Cortex_R5_0_0: GEL Output:    Config Matches
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 4 
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 5 
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 6 
    MAIN_Cortex_R5_0_0: GEL Output:    Not configured 
    MAIN_Cortex_R5_0_0: GEL Output: CPSW9G Port 7 
    MAIN_Cortex_R5_0_0: GEL Output:    ERROR: Expected: Mode: RMII, Actual: Mode: RGMII 
    MAIN_Cortex_R5_0_0: GEL Output: 

    3. cpsw_print_reg.gel

    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW 
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x02B40000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output:  CPSW 
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_NUSS_IDVER_REG            = 0x6BA00101
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_COUNT_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SYNCE_MUX_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_MODE_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: SUBSSYSTEM_STATUS_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RGMII_STATUS_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SGMII_IDVER_REG                = 0x4EC21102
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_RESET_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000030
    MAIN_Cortex_R5_0_0: GEL Output: MR_ADV_ABILITY_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_NP_TX_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_ADV_ABILITY_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MR_LP_NP_RX_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_CFG_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AUX_CFG_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CLEAR_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_CONTROL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: DIAG_STATUS_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MDIO_VERSION_REG               = 0x00070907
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x810000FF
    MAIN_Cortex_R5_0_0: GEL Output: ALIVE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LINK_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_RAW_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASKED_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_SET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_INT_MASK_CLEAR_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: MANUAL_IF_REG                  = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: POLL_REG                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLL_EN_REG                    = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: CLAUS45_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR0_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ADDR1_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_ACCESS_REG_0              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: USER_PHY_SEL_REG_0             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: REVISION                       = 0x6690A200
    MAIN_Cortex_R5_0_0: GEL Output: control                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EOI_REG                        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENABLE_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_EVNT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE0_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG_STAT_PULSE1_0       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_EVNT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE0_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_CLR_REG_STAT_PULSE1_0   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_EVNT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE0    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTR_VECTOR_REG_STAT_PULSE1    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPSW_ID_VER_REG                = 0x6BA80100
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EM_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: STAT_PORT_EN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PTYPE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: SOFT_IDLE_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THRU_RATE_REG                  = 0x00003001
    MAIN_Cortex_R5_0_0: GEL Output: GAP_THRESH_REG                 = 0x0000000B
    MAIN_Cortex_R5_0_0: GEL Output: TX_START_WDS_REG               = 0x00000008
    MAIN_Cortex_R5_0_0: GEL Output: EEE_PRESCALE_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_SET_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_OFLOW_THRESH_CLR_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_L_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_SET_H_REG      = 0xFFFFFFFF
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_L_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_G_BUF_THRESH_CLR_H_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_LTYPE_REG                 = 0x88A88100
    MAIN_Cortex_R5_0_0: GEL Output: EST_TS_DOMAIN_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI0_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI1_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI2_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI3_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI4_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI5_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI6_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: TX_PRI7_MAXLEN_REG             = 0x000007E8
    MAIN_Cortex_R5_0_0: GEL Output: P0_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FLOW_ID_OFFSET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: P0_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: P0_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_EEE_STATUS_REG              = 0x00000060
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_PKTS_PRI_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_GAP_REG                  = 0x01000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_FIFO_STATUS_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_RX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_A_REG                = 0x04030201
    MAIN_Cortex_R5_0_0: GEL Output: P0_SRC_ID_B_REG                = 0x08070605
    MAIN_Cortex_R5_0_0: GEL Output: P0_HOST_BLKS_PRI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RESERVED_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_CONTROL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAX_BLKS_REG                = 0x00001004
    MAIN_Cortex_R5_0_0: GEL Output: PN_BLK_CNT_REG                 = 0x00000001
    MAIN_Cortex_R5_0_0: GEL Output: PN_PORT_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CTL_REG                 = 0x00009000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_PRI_MAP_REG              = 0x76543210
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_MAXLEN_REG               = 0x000005EE
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_BLKS_PRI_REG             = 0x01245678
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_FLOW_THRESH_REG          = 0x00000040
    MAIN_Cortex_R5_0_0: GEL Output: PN_IDLE2LPI_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_LPI2WAKE_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_EEE_STATUS_REG              = 0x00000062
    MAIN_Cortex_R5_0_0: GEL Output: PN_FIFO_STATUS_REG             = 0x0000FF00
    MAIN_Cortex_R5_0_0: GEL Output: PN_EST_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_RX_DSCP_MAP_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_CIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_PRI_EIR_REG_y               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_L_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_SET_H_REG       = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_L_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_THRESH_CLR_H_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_L_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_SET_H_REG   = 0x1F1F1F1F
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_L_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_G_BUF_THRESH_CLR_H_REG   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_L_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TX_D_OFLOW_ADDVAL_H_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_L_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_SA_H_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_SEQ_LTYPE_REG            = 0x001E0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_VLAN_LTYPE_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL_LTYPE2_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_TS_CTL2_REG                 = 0x00040000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_CONTROL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_STATUS_REG              = 0xF0000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_SOFT_RESET_REG          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_BOFFTEST_REG            = 0x024F0000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_RXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_PAUSETIMER_REG       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TXN_PAUSETIMER_REG_y    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_EMCONTROL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PN_MAC_TX_GAP_REG              = 0x0000000C
    MAIN_Cortex_R5_0_0: GEL Output: FETCH_LOG_y (skipped)
    MAIN_Cortex_R5_0_0: GEL Output: ------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXCRCERRORS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXALIGNCODEERRORS              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOVERSIZEDFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXJABBERFRAMES                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXUNDERSIZEDFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXFRAGMENTS                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DROP                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_OVERRUN_DROP               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXGOODFRAMES                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXBROADCASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTICASTFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXPAUSEFRAMES                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXDEFERREDFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCOLLISIONFRAMES              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXSINGLECOLLFRAMES             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXMULTCOLLFRAMES               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXEXCESSIVECOLLISIONS          = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXLATECOLLISIONS               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RXIPGERROR                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXCARRIERSENSEERRORS           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TXOCTETS                       = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES64                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES65T127              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES128T255             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES256T511             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES512T1023            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: OCTETFRAMES1024TUP             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NETOCTETS                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_BOTTOM_OF_FIFO_DROP         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORTMASK_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: RX_TOP_OF_FIFO_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_RATE_LIMIT_DROP            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_VID_INGRESS_DROP           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_DA_EQ_SA_DROP              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_BLOCK_DROP                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_SECURE_DROP                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_AUTH_DROP                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_UNI_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_MLT_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_UNKN_BRD_BCNT              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_RED              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ALE_POL_MATCH_YELLOW           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TX_MEMORY_PROTECT_ERROR        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_REG_y           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_BCNT_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_REG_y      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: ENET_PN_TX_PRI_DROP_BCNT_REG_y = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x4E8A010A
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000004
    MAIN_Cortex_R5_0_0: GEL Output: RFTCLK_SEL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PUSH_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_EN_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_VAL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_LEN_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_RAW_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INTSTAT_MASKED_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: INT_ENABLE_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_NUDGE_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_POP_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_0_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_1_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_2_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: EVENT_3_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_LOAD_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_COMP_HIGH_VAL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_ADD_VAL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_LOW_VAL_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_PPM_HIGH_VAL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TS_NUDGE_VAL_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG_l                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG_l                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG_l                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG_l                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG_l                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_LOW_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: COMP_HIGH_REG                  = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: LENGTH_REG                     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_LOW_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PPM_HIGH_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: NUDGE_REG                      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: IDVER_REG                      = 0x00293904
    MAIN_Cortex_R5_0_0: GEL Output: STATUS_REG                     = 0x00000140
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL_REG                    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: CONTROL2_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PRESCALE_REG                   = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: AGING_TIMER_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_CONTROL_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD2_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD1_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: TABLE_WORD0_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: PORT_CONTROL_REG_y             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_MCAST_FLOOD_REG        = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: UNKNOWN_REG_MCAST_FLOOD_REG    = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: FORCE_UNTAGGED_EGRESS_REG      = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX0_REG             = 0x00000003
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX1_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX2_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX3_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX4_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX5_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX6_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MASK_MUX7_REG             = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PORT_OUI_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_DA_SA_REG              = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_VLAN_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_ETHERTYPE_IPSA_REG     = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_IPDA_REG               = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_PIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CIR_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TBL_CTL_REG            = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_CTL_REG                = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_TEST_CTL_REG           = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: POLICER_HIT_STATUS_REG         = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_DEF_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_CTL_REG                 = 0x00000000
    MAIN_Cortex_R5_0_0: GEL Output: THREAD_VAL_REG                 = 0x00000000
    

    Please help us to analyse if there is anything else we need to modify to fix the 9G sgmii port5 can't work issue. Looking forward to your reply.

    Thanks a lot.

    Lan

  • Hi All,

    We have started to look into issue now, there was some logistics to take care of which are now completed.

    You will get an update on this by tomorrow noon China time and then we will send another update by end of Friday.

    Regards
    Karthik

  • Hi,

    Can you please check the following registers in the memory browser in ccs. The gel scripts are printing incorrect values.

    • 0x0C000F08 (Alive register)
    • 0x0C000F0C (Link register)
    • 0x0C000510 (SGMII Control reg)
    • 0x0C000514 (SGMII Status reg)

    We have tested cpws9g code on port1 ,port2,port5 .  And  We have managed to make port 1,2 (as sgmii interfacework.

    Bus mac 5 (as sgmii interface  does not work.    the   cpsw0_sgmii5  status  reg show it not linked up / auto-neg never completed

    then code end in while loop wait for   sgmii  status reg  set.

    PHY  rtl9010aa  have verfied link up  for all the port.   

    What is the auto negotiation status in the phy registers? 

    I am currently trying to recreate a sgmii link from port 5 on my end. We can then compare and find out the issue for this.

    Regards,
    Tanmay

  • Hi Tanmay,

    Thank you for you reply.  I have checked the registers and the result is following:

    1.  The value of registers in the memory browser in ccs  is follwoing:

        0x0C000F08 (Alive register) -> 0x0000000F

        0x0C000F0C (Link register) -> 0x00000002

        0x0C000510 (SGMII Control reg) -> 0x00000001

       0x0C000514(SGMII Status reg) -> 0x00000030

    2. The auto negotiation status of RTL9010(phy) is disable.

     Regards,

    Lan

  • Hi,

    So the link register in cpsw shows that the link with phy 1, which is your desired phy, is up.

    2. The auto negotiation status of RTL9010(phy) is disable.

    So does that mean that you have disabled the auto negotiation with mac? Because as the link register is set, it indicates that the interface configuration is correct.

    We have tested cpws9g code on  mac2,mac5.  And  We have managed to make MAC2 (with sgmiiwork.

    As your MAC2 is working, lets start from there.

    1. You must have used 16G serdes (serdes 0) for this right?
    2. Can you confirm the changes between using MAC2 and MAC5? 
    3. Lets compare the following registers between both cases:
      1. PHY registers : all of them
      2. CPSW registers
        1. 0C000078h
        2. 0C000204h/0C000504h
        3. 0C000210h/0C000510h
        4. 0C000214h/0C000514h
        5. 0C000218h/0C000518h
        6. 0C000220h/0C000520h
        7. 0C000F04h
        8. 0C000F08h
        9. 0C000F0Ch
        10. 0C000F38h
        11. 0C023330h/0C026330h
        12. 0C023334h/0C026334h
        13. 0C023330h/0C026330h
        14. 0C023330h/0C026330h
        15. 0C023330h/0C026330h
        16. 0C023330h/0C026330h
        17. 0C023330h/0C026330h
      3. serdes registers
        1. 050004C0h/05050480h
        2. 050004C4h/05050484h
        3. 050004C8h/05050488h
        4. 050004CCh/0505048Ch
        5. 0500E000h/0505E000h
    4. Build the project in debug mode and compare the logs for both the cases.

    Please do reach out if you need any help for this.

    Note : Registers where single address is mentioned, are the port independent registers. Take value of the same register for both cases. 

    Regards,
    Tanmay

  • Hi,

    Also I wasn't able to find the register description for RTL9010 (PHY). Can you provide a datasheet for the same?

    Thanks and Regards,
    Tanmay

  • Hi Tanmay,

    Thank your for your timely response.

    So does that mean that you have disabled the auto negotiation with mac? Because as the link register is set, it indicates that the interface configuration is correct.

    =》Yes, we disabled the auto negotiation and set 1000M speed and Full Duplex to phy. the interface configuration is correct

    1. You must have used 16G serdes (serdes 0) for this right?

    =》Yes, correct.

    2. Can you confirm the changes between using MAC2 and MAC5? 

    3. Lets compare the following registers between both cases:

    a.  PHY registers : all of them

         The phy register of port 2 is the same as port3. As following:

    HY 1:  BMCR    = 0x0140                                                         
    PHY 1: BMSR    = 0x000d                                                         
    PHY 1: PHYIDR1 = 0x001c                                                         
    PHY 1: PHYIDR2 = 0xcb30                                                         
    PHY 1: ANAR    = 0x0000                                                         
    PHY 1: ANLPAR  = 0x0000                                                         
    PHY 1: ANER    = 0x0000                                                         
    PHY 1: ANNPTR  = 0x0000                                                         
    PHY 1: ANNPRR  = 0x0000                                                         
    PHY 1: CFG1    = 0x0000                                                         
    PHY 1: STS1    = 0x3000                                                         
    PHY 1: 1KSCR   = 0x0000
    

    b. CPSW registers 

    A.	0C000078h -> 0x00000003/0x00000000
    B.	0C000204h/0C000504h ->0x00000000/0x00000000
    C.	0C000210h/0C000510h -> 0x00000001/0x00000001
    D.	0C000214h/0C000514h -> 0x0000003D/0x00000030
    E.	0C000218h/0C000518h-> 0x00009801/0x00009801
    F.	0C000220h/0C000520h -> 0x0000D801/0x00000000
    G.	0C000F04h -> 0x41000090/0x41000090
    H.	0C000F08h -> 0x0000000f/0x0000000f
    I.	0C000F0Ch -> 0x00000008/0x00000002
    J.	0C000F38h -> 0xffffffff/0xffffffff
    K.	0C023330h/0C026330h -> 0x00040020/0x00040000
    L.	0C023334h/0C026334h -> 0xf0000018/0xf0000000
    

    c. serdes registers

    A.	050004C0h/05050480h -> 0x70800000/0x70800000
    B.	050004C4h/05050484h-> 0x00010002/0x00010002
    C.	050004C8h/05050488h-> 0x00000008/0x00000000 
    D.	050004CCh/0505048Ch -> 0x00000003/0x00000002
    E.	0500E000h/0505E000h -> 0x00002435/0x00490011 
    

    4. Build the project in debug mode and compare the logs for both the cases.

    a. log of port 2

    Enabling clocks!
    =======================================================
                CPSW Ethernet Firmware                     
    =======================================================
    CPSW_9G Test on MAIN NAVSS
    EnetPhy_bindDriver: PHY 3: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx' : OK
    PHY 0 is alive
    PHY 1 is alive
    PHY 2 is alive
    PHY 3 is alive
    ETHFW Version   : 0.01.01
    ETHFW Build Date: Jan  4, 2022
    ETHFW Build Time: 18:51:42
    ETHFW Commit SHA: e87bd0ad
    
    IPC_echo_test (core : mcu2_0) .....
    Remote demo device (core : mcu2_0) .....
    CpswMacPort_checkSgmiiStatus: MAC 2: SGMII link parter config port: link up: 1-Gbps Full-Duplex
    Cpsw_handleLinkUp: Port 2: Link up: 10-Mbps Half-Duplex
    Host MAC address: 70:ff:76:1d:92:c2
    [NIMU_NDK] ENET has been started successfully
    
    CPSW NIMU application, IP address I/F 1: 192.168.1.40
    
    EthFw: TimeSync PTP enabled
    Rx Flow for Software Inter-VLAN Routing is up
    

    b. log of port 5

    Enabling clocks!
    =======================================================
                CPSW Ethernet Firmware                     
    =======================================================
    ETHFW: Shared multicasts (software fanout):
      01:00:5e:00:00:01
      01:00:5e:00:00:fb
      01:00:5e:00:00:fc
      33:33:00:00:00:01
      33:33:ff:1d:92:c2
      01:80:c2:00:00:00
      01:80:c2:00:00:03
    ETHFW: Reserved multicasts:
      01:80:c2:00:00:0e
      01:1b:19:00:00:00                                                             
    EnetMcm: CPSW_9G on MAIN NAVSS                                                  
    PHY 0 is alive                                                                  
    PHY 1 is alive                                                                  
    PHY 2 is alive                                                                  
    PHY 3 is alive                                                                  
    EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'Rtl9010bx' : OK                                                                                   
    ETHFW Version   : 0.02.00                                                       
    ETHFW Build Date: Jan 17, 2022                                                  
    ETHFW Build Time: 19:13:52                                                      
    ETHFW Commit SHA:                                                               
    Starting lwIP, local interface IP is 192.168.1.30
    

  • Hi,

      we can't provide the datasheet of RTL9010.  Can you download it from the official website of REALTEK?

    Regards,

    Lan

  • HI Tanmay,

    We have sent the datasheet of RTL9010 to Juergen. Can you get it from him? Please contract us if there is anything else. Thank you.

  • Hi Lan,

    we disabled the auto negotiation

    So when is the phy negotiating with mac? I suggest you try once with the auto negotiation enabled.

    According to your register dump, the mdio link with phy is up but the sgmii link through serdes is not. So I think the serdes configuration might have issues. I am currently looking into this. I will provide you with an update as soon as possible.

    Regards,
    Tanmay

  • Hi Tanmay,

    I tried to set sgmii mode in phy chip to negotiation enabled/enable sgmii force mode.

     

    1. Negotiation enabled in RTL9010 and sgmii mode in TDA4 is  ENET_MAC_SGMIIMODE_SGMII_WITH_PHY. The register value in RTL9010 is following:

                reg addr             value

    PHY 1:  0xcf04      =      0xe000
    PHY 1:  0xcc04     =      0x7080
    PHY 1:  0xce0c     =      0x0096

    MDI is connected, but SGMII is not conneted.

    2. Enable sgmii force mode in RTL9010 and sgmii mode in TDA4 is ENET_MAC_SGMIIMODE_SGMII_WITH_PHY. The register value in RTL9010 is following:

                reg addr             value

    PHY 1:  0xcf04      =       0xf800
    PHY 1:  0xcc04     =       0x7180
    PHY 1:  0xce0c     =       0x0096

    MDI and SGMII are all connected.

    You can refer to the register description in the datasheet of RTL 9010.

    And for above two cases,  sgmii link through serdes is not link up.

    Thank you for your help, and please send massage to me if there is anything else need to check.

    Lan 

  • Unlocking this thread. TI is continuing to investigate, we have hit some roadblocks and working through it.

  • Hi Jinbao, Lan, 

    You can use the following tools for debug in linux :

    • General Info :
      • The linux console is available on 0th UART instance
      • The Ethfw logs are available on 2nd UART instance
      • Additionally, you can also get ethfw logs from running the command : `cat /sys/kernel/debug/remoteproc/remoteproc*/trace0`
      • The binary for ethfw should be loaded at [ROOTFS PARTITION]/lib/firmware/ethfw/app_remoteswitchcfg_server.xerf5
    • `ping $IP_ADDR` to test the connection from phy.
    • A lot of functionality is available using ethtool :
    • You can use ‘k3conf ‘ utility to checks clocks and other things related to system firmware. Type “k3conf --help” for a list of available commands.
    • You can use devmem2 to read/write the registers (Use the addresses available in TRM).
      • devmem2 $ADDR : to read register at address $ADDR
      • devmem2 $ADDR w $VALUE : to write $VALUE to address $ADDR
    • You can use phytol to read and write the phy registers. Refer this : https://github.com/wkz/phytool

     

    Thanks and Regards,

    Tanmay