This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA785: Figure 5-45. QSPI Read (Clock Mode 3) question

Part Number: DRA785

Hi Expert,

Regarding to the figure 5-45. QSPI Read (Clock Mode 3) of DRA78X datasheet, I have two questions as below.

1. There is missing Q8

2.It seems that sample signal at the falling edge of sclk , but in my understanding , it should be sample signal at the raising edge of sclk in the mode 3.

Could you please confirm ? Thanks! 

  • 1) Q8 does not apply to read mode.  Q8 is the time between D0 being tri-stated, and the CS rising edge.  In a read operation, that timing is controlled by the device being read from, not our device.

    2) The data is captured on the falling edge in both Mode 0 and Mode 3.  You are correct in saying that is not the norm.  See note 3 underneath table 5-48.