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AM3352: AM3352 DDR3L error and unstable with LCD bus function enable

Part Number: AM3352

Hi, TI experts

We used AM3352 and DDR3 in several projects before, and mass-produced them in years

Recently, We have built a board with AM3352 and DDR3L.. This is the first time we use DDR3L. 

We encounter the DDR error and random reboot issue in our system. This only happens when the LCD bus function is enable.

When we disable the LCD bus, the issue is gone. We have followed the latest EMIF document and spreadsheet to fine-tuned the parameters. 

But it didn't fixed that. We have tried to turn the DDR power back to 1.5V, and then it worked well again. 

We suspect that it might be the crosstalk in between LCD bus and DDR bus PCB.

But the LCD bus PINs of the IC are next to DDR DATA PINs, there is nothing we can do in the PCB layout.   

I wonder if it's a known issue or something I can dig deeper?  

-Andy

  • Were the layout guidelines in section 7.7.2.3 of the datasheet followed, especially with respect to the keepout region, clearances between DDR and non-DDR signals (see Table 7-63) and solid reference plane under the full keepout region.  The DDR and LCD signals are adequately separated on the package, and proper exit routing should allow adequate separation of the signals.  

    One debug idea is to send a switching pattern on all of the LCD pins, and then sequentially reduce the switching of the data signals one by one, to see if you can narrow down the offending signal(s).  The ultimate solution, however, may require a layout change.  

    Regards,

    James